Key Specs
| Spec | Value | Condition | Source |
|---|---|---|---|
| Channel Type | Independent | Digi-Key | |
| Current Peak Output Source Sink | 4A, 4A | Digi-Key | |
| Digikey Programmable | Not Verified | Digi-Key | |
| Driven Configuration | High-Side, Low-Side | Digi-Key | |
| Gate Type | MOSFET (N-Channel) | Digi-Key | |
| High Side Voltage Max Bootstrap | 90 V | Digi-Key | |
| Input Type | Non-Inverting | Digi-Key | |
| Logic Voltage Vil Vih | - | Digi-Key | |
| Mounting Type | Surface Mount | Digi-Key | |
| Number Of Drivers | 2 | Digi-Key | |
| Operating Temperature Range | -40°C ~ 125°C (TJ) | Digi-Key | |
| Package Case | 8-VDFN Exposed Pad | Digi-Key | |
| Rise Fall Time (Typ) | 45ns, 45ns | Digi-Key | |
| Supplier Device Package | PG-VDSON-8-4 | Digi-Key | |
| Voltage Supply | 8V ~ 17V | Digi-Key |
When To Use
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12V automotive rail → 5V @ 3A: The 90 V high-side bootstrap voltage rating provides sufficient margin for automotive load-dump transients on a 12V rail. A synchronous buck controller with a lower bootstrap rating risks MOSFET gate oxide breakdown under transient spikes, causing premature failure.
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High-side/low-side gate drive for dual half-bridge motor control @ 4A peak: Independent channels capable of sourcing and sinking 4A ensure fast switching with minimal shoot-through risk. Using a single-channel driver or one with lower peak current can cause slow transitions and shoot-through, increasing switching losses and thermal stress.
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Surface-mount PCB with tight thermal constraints, operating at 125°C junction: The 8-VDFN exposed pad package facilitates efficient heat dissipation at elevated junction temperatures. A similar driver in a plastic DIP or non-exposed pad package would face thermal runaway under continuous operation at this temperature.
When Not To Use
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Output current demand > 4A continuous: The 4A peak source/sink current rating disqualifies this part for sustained currents above 4A. Use a multi-phase buck controller instead to share current load and avoid thermal overload.
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Switching frequency requirement > 500kHz: The typical 45 ns rise/fall time and package parasitics limit performance above 500 kHz switching frequency. For high-frequency operation, choose a high-frequency buck controller designed for sub-20 ns transitions and minimal dead time.
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Input voltage within 1V of output voltage and low noise sensitive: The 8V to 17V supply voltage range and MOSFET gate drive make it unsuitable for low dropout or low-noise linear regulation. Use an LDO regulator instead to minimize output voltage ripple and noise.
Application Notes
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The switching node (SW) connected to the MOSFET source or drain must have minimal parasitic inductance to prevent voltage overshoot; keep SW traces short and use a low-inductance plane.
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Pins 3 and the logic input and output pin are noise-sensitive; route these signals away from high di/dt nodes and avoid running them parallel to switching traces to reduce false triggering.
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The exposed pad on the 8-VDFN package must be soldered directly to a large thermal pad with multiple vias to the ground plane for effective heat sinking.
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Bootstrap capacitor placement is critical: the capacitor should be located close to the high-side driver pin and supply to ensure stable 90 V bootstrap voltage under transient loads.
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Separate ground returns for the driver logic and power stages where possible to minimize ground bounce and maintain signal integrity.
Gotchas
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[Bootstrap voltage margin miscalculation]: Designers sometimes assume the 90 V bootstrap rating is continuous input voltage max rather than peak transient. Under severe inductive load switching, voltage spikes can exceed 90 V, causing gate oxide stress and device breakdown.
Fix: Measure switching node voltage spikes with a high-bandwidth scope and add snubber or clamp circuits to limit transients below 90 V. -
[Incorrect layout causing shoot-through]: Routing the high-side and low-side gate outputs without proper spacing or cross-coupling can induce crosstalk, causing simultaneous conduction of both MOSFETs. This results in shoot-through current spikes visible as current overshoot and excessive device heating.
Fix: Use short, well-separated gate traces with a ground guard trace between them and verify switching waveforms on both gates during bring-up. -
[Startup oscillation at minimum load]: Without a minimum load or proper gate drive timing, the driver can cause unstable switching or oscillation due to insufficient gate charge/discharge during startup, leading to output voltage ripple and erratic switching patterns on scope.
Fix: Add a small bleed resistor or dummy load on the output and verify startup waveforms with a low-inductance scope probe. -
[ESR interaction with gate drive]: Excessively high output capacitor ESR can feed back into the driver through the switching node, causing ringing and undervoltage on the gate drive signal. This manifests as intermittent switching and increased EMI.
Fix: Specify low-ESR ceramic capacitors near the driver and verify switching node waveform cleanliness during transient load steps.