Key Specs
| Spec | Value | Condition | Source |
|---|---|---|---|
| Channel Type | Single | Digi-Key | |
| Current Peak Output Source Sink | 4A, 4A | Digi-Key | |
| Digikey Programmable | - | Digi-Key | |
| Driven Configuration | High-Side | Digi-Key | |
| Gate Type | IGBT, SiC MOSFET | Digi-Key | |
| Grade | - | Digi-Key | |
| High Side Voltage Max Bootstrap | 650 V | Digi-Key | |
| Input Type | Non-Inverting | Digi-Key | |
| Logic Voltage Vil Vih | 0.8V, 2.4V | Digi-Key | |
| Mounting Type | Surface Mount | Digi-Key | |
| Number Of Drivers | 1 | Digi-Key | |
| Operating Temperature Range | -40°C ~ 125°C (TJ) | Digi-Key | |
| Package Case | 8-SOIC (0.154”, 3.90mm Width) | Digi-Key | |
| Qualification | - | Digi-Key | |
| Rise Fall Time (Typ) | 12ns, 12ns | Digi-Key | |
| Supplier Device Package | PG-DSO-8 | Digi-Key | |
| Voltage Supply | 10V ~ 22V | Digi-Key |
When To Use
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650 V high-side gate drive for SiC MOSFET in automotive inverter: The 650 V floating well offset supply voltage and 22 V maximum high-side supply voltage allow direct drive of high-voltage SiC MOSFET gates in automotive traction inverters. Lower-voltage or non-isolated drivers risk shoot-through or latch-up due to insufficient voltage margin or offset handling.
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Fast transient switching in industrial motor drives at 4A peak current: The 4 A peak output source and sink current combined with 12 ns typical rise/fall times and 80 ns propagation delays enable tight control of fast-switching IGBTs or MOSFETs, avoiding excessive switching losses and thermal runaway. Using a slower driver or one with lower peak current would cause excessive switching losses and possible device overheating.
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High transient immunity applications with up to 50 V/ns offset voltage slew rate: The 50 V/ns maximum allowable offset supply transient protects the driver’s floating well node from destructive voltage spikes in hard-switching environments. Controllers without such transient immunity can suffer latch-up or damage during rapid voltage transitions in hard-switched topologies.
When Not To Use
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Output current above 4 A continuous with high efficiency requirement: The 4 A peak driver current limits the maximum continuous current capability. For currents exceeding this, especially where efficiency is critical, use a high-current synchronous buck with external FETs instead.
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Battery-powered sensor node with ultra-low quiescent current demand: The typical quiescent current of 350 µA is too high for μA-level sleep-mode operation. Use a low-IQ PFM buck to minimize battery drain during standby.
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Switching frequency above 500 kHz for compact magnetics: The propagation delays and switching characteristics are optimized for typical frequencies below 500 kHz. For switching frequencies above 500 kHz, use a high-frequency buck controller designed for faster switching and reduced switching losses.
Application Notes
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The switching node (SW) and bootstrap capacitor must be placed close to the high-side driver pins to minimize parasitic inductance and voltage overshoot during fast switching transitions.
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CS (current sense) input is open-drain with a typical Rds(on) of -50 Ω at 2 mA; it requires a proper pull-up resistor and careful routing to avoid noise injection into the sensing line.
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Pins related to FLTC and RFE are sensitive to noise; guard routing and shielding are recommended to prevent false fault triggering.
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The high-side floating well offset supply voltage can swing up to ±650 V; ensure creepage and clearance distances on the PCB meet isolation requirements to prevent arcing.
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After any undervoltage event on VBS or VCC, an input logic edge is required to restart the driver, so the control firmware or logic must handle recovery sequencing explicitly.
Gotchas
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[Faulty undervoltage recovery sequencing]: Assuming the driver restarts automatically after a VBS or VCC undervoltage event without a new rising edge on HIN leads to a no-output condition. The driver requires a fresh input edge after UVLO clears. Symptom: output gate remains off despite supply recovery. Fix: implement logic to toggle HIN after supply recovers.
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[Incorrect CS line pull-up resistor sizing]: Using a too-low value pull-up on the open-drain CS input causes excessive current and distorts the current sense threshold, leading to false overcurrent triggers. Symptom: premature or spurious shutdowns under load. Fix: use recommended pull-up values matching the -50 Ω Rds(on) at 2 mA typical specified and verify CS threshold voltages in-system.
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[Noise coupling into FLTC pin]: Routing FLTC without guard traces or near high dV/dt nodes causes false fault latch triggering due to capacitive coupling. Symptom: unexpected fault conditions and shutdowns during normal operation. Fix: route FLTC away from switching nodes and use ground guard traces.
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[Thermal dissipation underestimated due to package limits]: Ignoring the 625 mW maximum package power dissipation and 200 °C/W junction-to-ambient thermal resistance causes junction overheating even if current limits are respected. Symptom: device junction temperature rapidly rising, leading to thermal shutdown or reliability degradation. Fix: perform thermal simulation including PCB copper area and heat sinking to keep junction below 150 °C max.