Estimate total MOSFET power dissipation and junction temperature for a hard-switched converter. Covers conduction loss (Id²·Rds(on)·D), switching loss approximated from gate charge and resistance, and gate drive loss (Qg·Vgs·fsw). All calculations in your browser.
MOSFET Power Loss & Junction Temperature
Switch Conditions
MOSFET Parameters (from datasheet)
Gate Drive
Thermal
Loss Component
Value
% of Ptotal
Conduction loss Pcond = Id²×Rds(on)×D
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--
Switching loss Psw(from Qg+Rg)
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--
Total MOSFET loss Ptotal
--
100%
Gate drive loss Pgate = Qg×Vgs×fsw(heats driver, not FET)
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—
Est. junction temp Tj
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Est. rise/fall time tr ≈ tf
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Formula & Theory
For a hard-switched MOSFET in a power converter, total dissipation has three components:
1. Conduction Loss
Pcond = Id² × Rds(on) × D
The MOSFET conducts for a fraction D of each switching period. For the high-side switch in a buck converter, D = Vout/Vin. Rds(on) must be the value at operating temperature — Si MOSFET Rds(on) approximately doubles from 25°C to 125°C.
2. Switching Loss
Energy is dissipated during each Vds/Id overlap transition:
Contrast with IRF540N (legacy TO-220, same conditions): Rds(on) = 77 mΩ, Qg = 71 nC → Pcond = 290 mW, Psw = 766 mW, Ptotal = 1.06 W — requires heatsink at 300 kHz.
Assumptions & Limitations
Linear switching waveforms — actual Vds/Id transitions are nonlinear due to MOSFET capacitances and parasitics. The formula can over- or under-estimate Psw by 2×.
No Qrr (body diode reverse recovery) — in hard-switched synchronous designs with Si MOSFETs, Qrr injects additional loss at high-side turn-on that can equal Psw. SiC and GaN devices have negligible Qrr.
Constant Id during switching — inductor current ripple means peak turn-on current is Iout + ΔIL/2, which slightly underestimates Psw.
Single MOSFET at a time — for synchronous designs, run twice: high-side at D, low-side at (1−D) with its own Rds(on).
θja is for still-air, no heatsink — actual thermal resistance depends strongly on copper pour, vias, and airflow. Use empirical measurement for designs above 1 W.
Rds(on) must be entered at operating temperature — use the datasheet Rds(on) vs. Tj curve. Si MOSFET Rds(on) approximately doubles from 25°C to 125°C.
Common Mistakes
Using 25°C Rds(on): The datasheet headline spec is at 25°C — actual Rds(on) at Tj = 100°C is 1.6–2× higher. Enter the value from the Rds(on) vs. Tj curve at your expected operating temperature.
Ignoring Qrr in synchronous Si designs: Body diode reverse recovery can add 50–500 mW of loss that this calculator omits. SiC or GaN eliminates Qrr loss entirely.
Omitting Rg,int: Even with no external gate resistor, every MOSFET has an internal gate resistance (0.5–5 Ω, listed as RG in the datasheet). A missing Rg,ext does not mean Rg,total = 0.
Applying θja with a heatsink attached: θja assumes no heatsink. With a heatsink, use θjc + θcs + θsa for the full thermal chain.
Neglecting copper pour area for SMD packages: For D2PAK and PowerPAK devices, the exposed pad soldered to PCB copper is the primary thermal path. 1 cm² of outer-layer copper reduces effective θja by ~20–30°C/W compared to the datasheet value.
Next step: choose real parts
Use the calculated loss and junction temperature to narrow your MOSFET selection. Key datasheet specs to verify are listed below for each component category.
1. Power MOSFET
Vds,maxMust exceed Vds × 1.3 minimum — PCB inductance causes transient spikes. Use 40 V devices for 12 V rails, 80 V for 24 V, 100 V for 48 V systems.
Rds(on) at TjCheck the Rds(on) vs. Tj curve at your expected operating temperature. The 25°C spec can be 50–100% lower than actual. If Pcond dominates your loss budget, lower Rds(on) is the lever.
Qg and QgdLower Qg reduces Psw and Pgate. Qgd (Miller charge) most directly sets switching speed. SiC and GaN devices have significantly lower Qgd than equivalent-voltage Si MOSFETs.
PackageD2PAK / LFPAK56 / PowerPAK give better PCB thermal performance than TO-220 via exposed pad soldering. Kelvin-source packages (separate gate-return pin) improve high-frequency switching behavior.
Peak source/sink currentDrive current sets tr/tf: Idrive = Vgs/Rg,total. For tr < 5 ns, you need ≥ 2 A peak. Standard half-bridge drivers: 1–6 A.
Driver power dissipationThe driver dissipates Pgate = Qg × Vgs × fsw. Small SOT-23 packages are typically rated for <200–300 mW — verify against the Pgate value from the calculator.
Bootstrap vs. isolatedBootstrap high-side drivers require the low-side switch to conduct briefly each cycle to refresh the bootstrap capacitor. At duty cycles above ~95%, bootstrap refresh fails. Use isolated drivers or charge-pump designs for near-100% duty cycles.
PCB copper pourFor SMD packages (D2PAK, PowerPAK), PCB copper is the primary thermal path. A 1 cm² outer-layer pour ≈ 20–30°C/W. Stitch to inner layers through multiple thermal vias for lower resistance.
Heatsink (through-hole)For TO-220 / TO-247 packages, clip-on heatsinks dramatically reduce Tj. Select on θsa value. Total resistance: Tj = Tamb + P × (θjc + θcs + θsa). Requires thermal interface material.
Interface materialThermal pads (θcs ≈ 0.5–1°C/W/cm²) or compound fills microscopic air gaps between MOSFET case and heatsink. Phase-change pads are preferred over grease in production for consistent assembly.
Psw > PcondIf switching loss dominates, Si is the wrong material. SiC MOSFETs (650 V–3.3 kV) have 3–5× lower Qgd. GaN HEMTs (100–650 V) add near-zero Qrr. Both cut Psw dramatically at the same frequency.
High frequency (> 500 kHz)Above 500 kHz, Si MOSFET switching loss makes the design thermally uncompetitive. GaN enables 1–5 MHz designs with practical efficiency, allowing dramatically smaller passives.
Gate drive caution for GaNGaN HEMTs require specialized drivers with tight Vgs control: typical turn-off at −3 V, turn-on at +5 to +6 V. Standard Si gate drivers will damage or inefficiently drive GaN devices. Use manufacturer-specific gate driver ICs only.
Distributor links are referral links. Prices and availability sourced from distributor sites at time of search. Verify all specs against current manufacturer datasheets before ordering.
When this calculator is not enough
Qrr reverse recovery: Hard-switched synchronous Si designs have significant Qrr loss that this calculator does not model. It can equal Psw for slow Si MOSFETs. Use a SPICE model with accurate Qrr parameters, or switch to GaN/SiC to eliminate it.
Dead-time body diode loss: During dead time, the body diode conducts at Vf ≈ 0.6–1.2 V. For long dead times (50+ ns) at high frequency, this adds meaningful loss. This calculator assumes ideal dead time control.
PCB parasitic inductance: Gate loop inductance causes ringing and shifts actual rise/fall times. Power loop inductance causes Vds overshoot beyond Vin. Minimize loop area on the PCB — this is a layout constraint, not just a component selection issue.
Thermal coupling between adjacent devices: In multi-MOSFET designs, adjacent devices thermally couple through the PCB and raise each other's operating temperature. Run a thermal simulation for high-density power stages.
Safe operating area (SOA): The SOA curve limits permissible Vds/Id combinations during startup, overcurrent, and avalanche events. Verify your worst-case operating point lies within the MOSFET SOA at your expected Tj.
Rds(on) self-consistency: The Rds(on) you enter sets Pcond, which sets Ptotal, which sets Tj, which changes Rds(on). For accurate results, iterate: enter an initial Rds(on), note the Tj, look up Rds(on) at that Tj, re-enter, and repeat until Tj converges.
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What is MOSFET conduction loss and how is it calculated?
Conduction loss occurs while the MOSFET channel is fully on. For a high-side switch in a buck converter: Pcond = Id² × Rds(on) × D, where D is the duty cycle. Rds(on) increases ~2× from 25°C to 125°C for Si MOSFETs — always use the hot Rds(on) from the datasheet Rds vs Tj curve, not the 25°C headline spec.
How is switching loss estimated from gate charge?
Switching loss per transition is approximated as ½ × Vds × Id × (tr + tf) × fsw. Rise/fall times are estimated from gate charge: tr ≈ tf ≈ Qg × Rg_total / Vgs_drive. This gives Psw ≈ Vds × Id × Qg × Rg × fsw / Vgs_drive. This is a linear approximation — body diode reverse recovery (Qrr) is not included.
What is gate drive power loss?
Gate drive loss is the power to charge/discharge the gate capacitance each cycle: Pgate = Qg × Vgs × fsw. This heats the gate driver IC and gate resistor — not the MOSFET die. At 20 nC, 10 V drive, 300 kHz: Pgate = 60 mW. Small SOT-23 gate drivers cannot handle more than ~200–300 mW.
Why does this calculator cover one MOSFET at a time?
In a synchronous buck, the high-side conducts for D of the cycle and the low-side for (1−D). They may have different Rds(on) values. Run the calculator twice — once for each device — for accurate total loss. For an asynchronous design, run it once for the switch only.
How accurate is the junction temperature estimate?
Tj = Tamb + Ptotal × θja is a worst-case estimate using the datasheet θja (still air, specific test PCB). With copper pours, heatsinks, or airflow, actual Tj will be lower. For designs carrying >2 A, measure PCB temperature empirically or use thermal simulation. The result here is a conservative upper bound.
When should I use SiC or GaN instead of Si?
Switch to SiC or GaN when Psw > Pcond — meaning switching loss dominates. SiC MOSFETs (650 V–3.3 kV) have 3–5× lower Qgd than equivalent Si, cutting switching loss significantly. GaN HEMTs (100–650 V) add near-zero Qrr, ideal for >500 kHz designs. Both require careful gate drive design — GaN in particular needs specialized drivers (typically −3 V / +5 V gate swings).