Buck Converter Inductor & Capacitor Sizing Calculator

Calculate minimum inductance (Lmin), output capacitance (Cout), duty cycle, and peak inductor current for a synchronous buck converter in CCM. Handles Vin min/max for worst-case design. All values computed in your browser.

Buck Converter — Inductor & Output Capacitor Sizing

Input Voltage

V_in,min (V) V_in,max (V)

Output & Load

V_out (V) I_out (A)

Frequency & Ripple Spec

f_sw (kHz) Ripple ratio % ΔV_out,max (mV)

Parameter	@ V_in,min	@ V_in,max
Duty Cycle D	--	--
L_min (worst case at V_in,max)	--	--
Ripple Current ΔI_L	--	--
Peak Inductor Current I_L,pk (= I_sat budget)	--	--
C_out,min	--

Formula & Theory

For a synchronous buck in CCM, the critical design equations are:

Duty cycle: D = V_out / V_in
Ripple current: ΔI_L = K_r × I_out where K_r is the ripple ratio (typically 0.2–0.4)
Minimum inductance (worst case at V_in,max):
L_min = (V_in − V_out) × V_out / (V_in × ΔI_L × f_sw)
Peak inductor current (= saturation rating requirement):
I_L,pk = I_out + ΔI_L / 2
Output capacitor (ESR-limited ripple):
C_out,min = ΔI_L / (8 × f_sw × ΔV_out)

L_min is maximized at V_in,max — design the inductor to the worst-case input. ΔI_L is specified as a fraction of I_out, so it stays constant with V_in for a fixed ripple ratio. C_out is independent of V_in for a fixed ΔI_L spec.

The CCM/DCM boundary occurs when ΔI_L ≥ 2 × I_out (ripple ratio ≥ 200%). Below the CCM boundary load current (I_out,crit = ΔI_L/2), the converter enters DCM.

Worked Example

Design target: 9–15 V input → 5 V at 3 A output, f_sw = 300 kHz, 30% ripple ratio, ΔV_out ≤ 50 mV.

ΔI_L = 0.30 × 3 A = 0.9 A pk-pk
D @ V_in,min = 5/9 = 55.6%
D @ V_in,max = 5/15 = 33.3%
L_min @ 9 V = (9−5)×5 / (9×0.9×300,000) = 8.23 µH
L_min @ 15 V = (15−5)×5 / (15×0.9×300,000) = 12.35 µH ← worst case
I_L,pk = 3 + 0.45 = 3.45 A → select inductor with I_sat ≥ 4.1 A (1.2× margin)
C_out,min = 0.9 / (8 × 300,000 × 0.05) = 7.5 µF → use 2× 10 µF 0805 MLCC in parallel

Practical choices: 15 µH shielded inductor (Bourns SRR1260 or Würth 744066150), 2× 10 µF 50 V 0805 MLCC (GRM21BR61H106KE43), TPS54325 or LM2596-5.0 for the IC.

Assumptions & Limitations

CCM only — if ΔI_L ≥ 2×I_out (ripple ratio ≥ 200%), the converter enters DCM and L_min is meaningless
ESR-dominated ripple — C_out formula assumes ESR×ΔI_L is the dominant ripple term; low-ESR MLCCs may allow smaller C_out but verify ESR×ΔI_L < ΔV_out
No MLCC DC bias derating — a 10 µF 0805 MLCC at 5 V may measure 3–5 µF; verify effective capacitance in the datasheet's DC bias curve and parallel additional caps as needed
Ideal switches — no dead-time body diode conduction, no switch voltage drops; real designs lose a few percent efficiency to these effects
No temperature derating — derate L by 20–30% for DC bias saturation degradation and 10–15% for temperature-dependent core losses
Continuous load — these formulas assume rated load throughout; light-load DCM entry is not modeled

Common Mistakes

Choosing L exactly at L_min: Add 20–50% margin (e.g. choose 15 µH when calculated value is 12.35 µH). At minimum L, component tolerances and Vin variation push the converter into DCM at light loads.
Confusing rated current with saturation current: An inductor's rated current spec is for thermal (RMS), not saturation. The saturation current (I_sat) must exceed I_L,pk. Use I_L,pk × 1.2 as the minimum I_sat rating to select.
Ignoring MLCC DC bias derating: A 10 µF 0805 50 V MLCC at 5 V DC bias can measure 3–4 µF. Use larger case sizes (1206, 1210) or place multiple caps in parallel.
Using electrolytic output capacitors above 100 kHz: Electrolytic ESR is too high at switching frequency — the entire ΔV_out budget is consumed. Use MLCC (low ESR) or polymer capacitors.
Forgetting high-side bootstrap capacitor: Most synchronous buck ICs require a 100 nF bootstrap capacitor from BOOT to SW. Omitting or under-sizing it causes driver shoot-through at high duty cycles.
Ignoring minimum on-time at high V_in / low duty cycle: At V_in,max the minimum on-time (typically 50–200 ns) of the IC may prevent regulation. Verify: V_out/V_in,max × (1/f_sw) ≥ t_on,min.

Next step: choose real parts

Use the calculated values above to filter the distributor catalogs. Each section below translates calculator outputs into the specific datasheet specs to verify.

1. Power Inductor

Inductance ≥ L_min at V_in,max, multiplied by 1.3 safety factor. Round up to next standard E12 value (10, 12, 15, 18, 22, 27, 33 µH…)

Saturation current I_sat Must exceed I_L,pk × 1.2. This is the spec that limits peak load current — don't confuse with rated current (thermal).

DC resistance (DCR) Lower DCR = lower conduction loss. At 3 A, 50 mΩ DCR = 450 mW dissipation. Target <30 mΩ for power-dense designs.

Package Shielded construction (e.g. SRR, SRH, WE-HCI) keeps EMI contained. Unshielded drum cores are cheaper but require more PCB copper pour for shielding.

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2. Output Capacitor

Capacitance Use ≥ C_out,min × 2–3 to account for MLCC DC bias derating. Verify effective capacitance from the cap's DC bias curve at your output voltage.

ESR at f_sw Verify ESR × ΔI_L < ΔV_out at your switching frequency. MLCC ESR is typically 1–10 mΩ — far better than electrolytic (50–200 mΩ).

Voltage rating Use a cap rated ≥ V_out × 2. MLCC capacitance degrades under voltage — a 25 V cap at 5 V output retains near-nominal capacitance.

Dielectric Use X5R or X7R MLCCs. Y5V and Z5U dielectrics have up to 80% capacitance loss with temperature and DC bias — avoid for power supply filtering.

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3. Input Capacitor & Layout

Input cap minimum C_in ≈ I_out × D × (1−D) / (f_sw × ΔV_in,ripple). In practice: 10–47 µF ceramic at the IC V_in pin is the starting point for most ≤5 A designs. Place it as close to the IC pin as possible.

Input RMS current The input cap carries pulsed current: I_rms ≈ I_out × √(D × (1−D)). At 3 A / 33% duty cycle this is ≈ 1.0 A RMS. Verify the capacitor ripple current rating — an undersized cap will overheat.

DC bias derating Input MLCCs at high V_in suffer severe capacitance loss. A 10 µF 16 V 0805 cap at 12 V may retain only 2–3 µF. Use caps rated ≥ V_in,max × 2 and check the DC bias curve in the datasheet.

Local 100 nF decoupling Place a 100 nF ceramic cap directly across the IC V_in/GND pins (within 2–3 mm). This absorbs high-frequency spikes that bulk MLCCs cannot handle due to series inductance at MHz frequencies.

Hot-loop layout The high-side switch drain → SW node → low-side source → input cap forms the "hot loop" carrying pulsed current at I_L,pk. Minimize the enclosed PCB area of this loop to limit radiated EMI and switching node ringing. The input cap must be adjacent to the IC, not routed across the board.

Follow IC datasheet Always use the IC-specific application schematic. Datasheet layout notes for bootstrap cap placement, SW node pour, EN/PGOOD pull-ups, and soft-start override any generic guidance above.

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4. Buck Regulator / Controller IC

Input voltage range Must span V_in,min to V_in,max with margin. Look for absolute max V_in rating ≥ V_in,max × 1.2.

Output current For an integrated regulator (not controller), the current limit must exceed I_L,pk. For controllers, size external MOSFETs to I_L,pk.

Switching frequency range The IC's f_sw range must include your target frequency. Fixed-frequency ICs are simpler; adjustable-frequency ICs allow optimization.

Synchronous vs asynchronous Synchronous (integrated low-side FET) is more efficient above ~1 A. Asynchronous requires an external Schottky diode but is simpler and immune to shoot-through during input power removal.

Compensation Voltage-mode ICs require external compensation network (R/C on COMP pin). Current-mode ICs are easier to compensate — a good choice for prototyping.

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Distributor links are referral links. Prices and availability sourced from distributor sites at time of search. Verify all specs against current manufacturer datasheets before ordering.

Component Spec Database

Datasheet references and comparisons for parts commonly used in buck converter designs:

When this calculator is not enough

Compensation design: This calculator assumes CCM steady-state — it does not design the control loop. Current-mode ICs are easier to compensate, but voltage-mode and COT/PFM architectures need frequency-domain analysis (Type II/III compensation, phase margin verification). Use your IC datasheet's step-by-step compensation procedure or a SPICE model.
Transient response: The C_out formula minimizes steady-state ripple, not load-step droop. For a requirement like ΔV_out ≤ 50 mV for a 3 A load step, the required capacitance can be much larger: C_tran ≥ I_step × t_response / ΔV_tran. Add bulk capacitance until transient response meets spec.
Thermal limits: Switching and conduction losses in the high-side MOSFET, low-side MOSFET (or catch diode), and inductor DCR all generate heat. Use the MOSFET Power Loss Calculator to estimate junction temperature rise, and verify against the package thermal resistance (θ_JA).
EMI / EMC compliance: This calculator does not model radiated or conducted emissions. For FCC Part 15 or CISPR 32 compliance you will need spread-spectrum or frequency dithering, an input EMI filter, proper layout (hot-loop area, star-ground placement), and EMI pre-scan testing before submission.
Discontinuous conduction mode (DCM): Below the critical load current (I_out,crit = ΔI_L/2), the converter enters DCM. In DCM, output voltage regulation depends on load and frequency — the L_min formula does not apply. Use your IC's DCM equations or a SPICE model.
Synchronous vs asynchronous differences: Asynchronous designs (external Schottky catch diode) have different dead-time requirements, minimum on-time constraints, and reverse-recovery loss that are not modeled here.
Regulator-specific constraints: Frequency-setting resistors, VREF trim, soft-start timing, enable sequencing, UVLO thresholds, and power-good delay are all IC-specific. Always start from the IC application schematic and use these sizing values only to sanity-check the magnetics.

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Frequently Asked Questions

What ripple ratio should I use for a buck converter?

A ripple ratio (ΔIL/Iout) of 20–40% is typical for CCM operation. Lower ratios (10–20%) reduce core loss and improve transient response but require a larger inductor. Ratios above 50% approach the CCM/DCM boundary and increase RMS current stress on the output capacitor.

Why do I need both Vin min and Vin max?

Worst-case inductance occurs at maximum Vin — the inductor must absorb more volt-seconds per cycle at high input voltage for the same output ripple. Worst-case duty cycle occurs at minimum Vin (highest D). Designing to Vin_max for L and Vin_min for duty cycle ensures the converter operates correctly across the full input range.

What is inductor saturation current and why does it matter?

Saturation current is the DC + peak current at which the inductor's inductance drops by a specified amount (typically 20–30%). If the peak inductor current (IL_pk = Iout + ΔIL/2) exceeds the saturation rating, inductance collapses, ripple spikes, and the converter may fail to regulate. Always select an inductor with Isat ≥ IL_pk × 1.2 for margin.

Why does Cout seem large compared to what's on existing boards?

This formula (Cout = ΔIL / (8 × fsw × ΔVout)) gives the capacitance needed when ESR dominates ripple. In practice, if you use low-ESR MLCCs, the actual required bulk capacitance may be smaller — but you must separately verify that ESR × ΔIL < ΔVout. MLCC capacitance also derate significantly under DC bias: a 10 µF 0805 cap may measure only 3–4 µF at 5 V.

What switching frequency should I choose?

200–500 kHz is a common starting point for 5–20 V rails at moderate currents. Higher frequency (500 kHz–2 MHz) allows smaller passives but increases switching losses, especially in the high-side MOSFET. Above 1 MHz, PCB layout parasitics dominate — trace inductance and ringing become design constraints.

Does this calculator work for DCM operation?

No — all formulas assume Continuous Conduction Mode (CCM). The converter enters DCM when ΔIL ≥ 2 × Iout (ripple ratio ≥ 200%). In DCM, the effective inductance is irrelevant for ripple calculation and output voltage regulation depends on load. For DCM-aware design, use your IC's datasheet equations or simulation.

Should I use a synchronous or asynchronous (diode) buck?

Synchronous designs (low-side MOSFET replaces the catch diode) are more efficient above ~1 A output because MOSFET Rds(on) loss is lower than diode forward drop. Asynchronous designs are simpler and tolerate input power removal without shoot-through risk. Below 500 mA or in battery-powered designs where low quiescent current matters, an asynchronous design with a Schottky diode may be preferred.

How much margin should I add to the calculated Lmin?

Add 20–50% margin. At exactly Lmin, any Vin variation, component tolerance, or load step that momentarily increases ΔIL will push the converter into DCM. A 30% margin (choose next standard value above 1.3 × Lmin) is a practical starting point. Standard inductor values follow an E12 or E24 series; round up to the next standard value after applying your margin.