Key Specs
| Spec | Value | Condition | Source |
|---|---|---|---|
| Technology | Capacitive Coupling | Digi-Key | |
| Number Of Channels | 1 | Digi-Key | |
| Voltage Isolation | 4000Vrms | Digi-Key | |
| Common Mode Transient Immunity (Min) | 100V/ns | Digi-Key | |
| Propagation Delay Tplh Tphl (Max) | 90ns, 90ns | Digi-Key | |
| Pulse Width Distortion (Max) | 20ns | Digi-Key | |
| Rise Fall Time (Typ) | 30ns, 30ns | Digi-Key | |
| Current Output High Low | 4A, 4A | Digi-Key | |
| Current Peak Output | 4A | Digi-Key | |
| Voltage Forward Vf (Typ) | - | Digi-Key | |
| Voltage Output Supply | 16.4V ~ 26V | Digi-Key | |
| Operating Temperature Range | -40°C ~ 125°C (TJ) | Digi-Key | |
| Mounting Type | Surface Mount | Digi-Key | |
| Package Case | 8-SOIC (0.154”, 3.90mm Width) | Digi-Key | |
| Supplier Device Package | 8-SO | Digi-Key | |
| Approval Agency | UL | Digi-Key |
When To Use
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400V isolated gate drive @ 4A peak: The 4000Vrms isolation rating combined with 4A peak driver current makes this ideal for driving high-voltage SiC MOSFET gates in isolated topologies, where robust galvanic isolation and high transient immunity (±100 V/ns) prevent latch-up and false triggering under dv/dt stress. Using a non-isolated driver or one with lower isolation would risk device damage from high-voltage surges or shoot-through.
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Fast switching SiC or GaN FET gate drive at up to 1 MHz: The 30 ns rise/fall times and ≤90 ns propagation delay enable clean, fast switching transitions critical for wide bandgap devices. Slower drivers or those with higher propagation delays cause excessive switching losses and increased thermal stress, potentially leading to thermal runaway.
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Industrial systems requiring UL 1577 recognized isolation: The UL recognition and strict creepage/clearance distances (≥4 mm) ensure compliance with safety standards for reliable isolation in harsh environments. Drivers without this certification risk regulatory non-compliance and catastrophic failure due to insulation breakdown or tracking.
When Not To Use
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Output current > 4A continuous: The 4A max driver current limits the gate charge drive capability for larger MOSFETs or parallel FET arrays. Use a high-current synchronous buck with external FETs instead, which can provide higher gate currents and reduce switching losses without overstressing the driver.
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Switching frequency beyond 1 MHz: The driver max switching frequency is 1 MHz; beyond this, propagation delay and pulse width distortion degrade performance. Use a high-frequency buck controller designed for >500 kHz switching to maintain timing integrity and avoid excessive switching losses.
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Low-dropout linear regulation with <1V differential: The gate driver voltage supply range (16.4 V to 26 V) and quiescent currents are unsuitable for low-dropout applications where noise and power dissipation are critical. Use an LDO regulator instead for clean, low-noise output with minimal dropout.
Application Notes
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The driver output stage can source and sink 4A peak current; place the gate driver as close as possible (<10 mm) to the power transistor gate to minimize parasitic inductance and ringing on the switching node (SW).
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Input logic pins (IN+, IN-) have 3.3 V to 5 V TTL/CMOS hysteresis; install small ceramic bypass capacitors (100 nF to 1 µF) as close as possible (within 1 mm) to these pins to filter high-frequency noise and prevent false triggering.
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Maintain a minimum clearance and creepage distance of 4 mm between input and output sides on the PCB to meet isolation requirements and avoid tracking failures; routing should avoid sharp bends and keep creepage paths as short as possible.
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Use a low-ESR SMT capacitor (1 µF to 10 µF) near the driver supply pins (VDD logic and VH positive supply) to ensure stable voltage during transient switching events; this reduces voltage dips that cause timing jitter or undervoltage lockout.
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Guard traces connected to chassis ground should be routed around the isolation barrier edges to reduce leakage currents and improve common-mode transient immunity (≥100 V/ns).
Gotchas
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[Ignoring gate driver supply undervoltage lockout]: Designers may assume the driver will operate down to VH supply voltages below 16.4 V, but the UVLO threshold is 14.6 V minimum with hysteresis. Operating near or below this threshold causes intermittent driver shutdown and erratic gate drive signals, visible as missing or delayed gate pulses on scope. Fix by ensuring VH supply remains above 16.4 V under all load and transient conditions with margin.
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[Underestimating pulse width distortion impact at high frequency]: At switching frequencies near 1 MHz, the fixed maximum pulse width distortion of 20 ns can cause timing skew between rising and falling edges, leading to increased shoot-through risk and distorted gate waveforms. This can manifest as abnormal switching losses and thermal hotspots. Mitigate by derating switching frequency below 1 MHz or adding gate resistors to slow transitions if ringing occurs.
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[Placing decoupling capacitors too far from pins]: The requirement to place 100 nF to 10 µF SMT capacitors as close as possible to the driver pins is often overlooked; capacitors >5 mm away allow supply voltage dips during switching transients, causing gate voltage undershoot and driver undervoltage triggers. Symptoms include jittery switching and occasional output glitches. Use shortest possible PCB traces and place capacitors on the same PCB layer adjacent to device pins.
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[Neglecting input-output isolation creepage]: Some layouts route input and output traces closer than 4 mm, violating creepage requirements. This leads to partial discharge and insulation degradation over time, eventually causing sudden insulation failure and potential gate driver destruction. Confirm PCB layout spacing with precise measurement tools and follow recommended isolation group material guidelines.