Key Specs
| Spec | Value | Condition | Source |
|---|---|---|---|
| Technology | Capacitive Coupling | Digi-Key | |
| Number Of Channels | 1 | Digi-Key | |
| Voltage Isolation | 4800Vpk | Digi-Key | |
| Common Mode Transient Immunity (Min) | 100V/ns | Digi-Key | |
| Propagation Delay Tplh Tphl (Max) | 90ns, 90ns | Digi-Key | |
| Pulse Width Distortion (Max) | 20ns | Digi-Key | |
| Rise Fall Time (Typ) | 30ns, 30ns | Digi-Key | |
| Current Output High Low | 4A, - | Digi-Key | |
| Current Peak Output | - | Digi-Key | |
| Voltage Forward Vf (Typ) | - | Digi-Key | |
| Voltage Output Supply | 3.1V ~ 5.5V | Digi-Key | |
| Operating Temperature Range | -40°C ~ 125°C (TJ) | Digi-Key | |
| Mounting Type | Surface Mount | Digi-Key | |
| Package Case | 8-SOIC (0.154”, 3.90mm Width) | Digi-Key | |
| Supplier Device Package | 8-SO | Digi-Key | |
| Approval Agency | UL, VDE | Digi-Key |
When To Use
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High-voltage isolated gate drive → 1700 V MOSFET gate: The 4800 V isolation rating combined with 100 V/ns common-mode transient immunity makes this part ideal for driving high-voltage MOSFET gates in isolated half-bridge or full-bridge topologies. A non-isolated driver or one with lower CMTI would risk latch-up or false switching under fast dv/dt conditions causing shoot-through or device failure.
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3.3 V to 5 V logic input control → 4 A gate drive current: The 4 A peak output current and 3.1 V to 5.5 V logic supply range perfectly match modern low-voltage digital control while supplying strong gate drive current for fast switching transitions. Using a driver with lower peak current capability risks slow gate charging, increasing switching losses and thermal stress on the power MOSFET.
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Surface mount isolated driver in compact industrial inverter: The 8-SOIC package with creepage ≥4 mm and UL/VDE approvals supports compact PCB layouts with certified isolation barriers. Using a bulky or non-certified package risks failing safety standards or requiring larger creepage distances, which increases board size and cost.
When Not To Use
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Output current > 4 A continuous: The maximum driver sink/source current is 4 A typical, which limits driving very large MOSFETs or multiple parallel devices. Use a high-current synchronous buck with external FETs controller that can handle higher gate charge and current demands.
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Switching frequency > 1 MHz: The maximum switching frequency rating is 1 MHz. Applications requiring faster switching for inductor size reduction or EMI mitigation need a high-frequency buck controller designed for >500 kHz operation.
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Low dropout linear regulation or noise-sensitive analog supplies: This device is a gate driver with no linear regulation capability and no low-noise reference. For low noise and small input/output differential (<1 V), use an LDO regulator.
Application Notes
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Place the 100 nF ceramic capacitor as close as possible between VDD and GND pins (pins 4 and 5) to minimize high-frequency noise on the logic supply line and maintain stable logic operation.
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The high-voltage supply VH and GNDISO pins must have a low-impedance bypass capacitor (1–10 µF) mounted close to the device to stabilize the floating supply and prevent voltage overshoot during switching transients.
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Avoid any copper traces or large conductive areas directly beneath the STGAP2SICSNCTR to reduce capacitive coupling and noise injection into the isolation barrier.
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Use adequate via sizes and place them close to the IC pins to minimize parasitic inductance and resistance, ensuring clean gate drive signals, especially critical for the high di/dt gate drive outputs.
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The propagation delay and pulse width distortion are sensitive to layout parasitics; keep gate driver output traces short and matched to reduce rise/fall time degradation and avoid timing mismatch in bridge configurations.
Gotchas
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[Ignoring UVLO hysteresis during startup]: The undervoltage lockout (UVLO) on the VH supply has a hysteresis of approximately 750 mV. If the supply ramp is slow or noisy near the threshold (15 V nominal), the driver may cycle unpredictably between on/off states, causing gate oscillation or partial switching visible as jitter on the gate waveform.
Fix: Use a clean, monotonic supply ramp above 16.4 V or add a supply supervisor circuit with hysteresis and adequate filtering. -
[Assuming input logic thresholds scale linearly with VDD]: Input logic thresholds are specified as fractions of VDD (e.g., VIH_typ = 0.66·VDD), but input bias currents (up to 50 µA at logic ‘1’) can cause voltage drop on high-impedance input signals, leading to undefined input states and intermittent switching.
Fix: Drive inputs with low-impedance logic signals and verify input voltage with scope under load conditions. -
[Overlooking the minimum deglitch filter time]: The deglitch filter minimum is 20 ns, but input signals with fast glitches narrower than this can still propagate through, causing false triggering or spurious gate pulses.
Fix: Add external input filtering or ensure input signals have minimum pulse widths longer than 40 ns for reliable operation. -
[Incorrect placement of bypass capacitors]: Placing the 1 µF to 10 µF bypass capacitor too far from the VH and VDD pins increases voltage overshoot and ringing on the floating supply rails, visible as oscillations on gate drive waveforms and potential false turn-on/off events.
Fix: Place all bypass capacitors within 2 mm of the respective pins with short, wide traces and low-inductance vias.