Key Specs
| Spec | Value | Condition | Source |
|---|---|---|---|
| Channel Type | Independent | Digi-Key | |
| Current Peak Output Source Sink | 1A, 1A | Digi-Key | |
| Digikey Programmable | Not Verified | Digi-Key | |
| Driven Configuration | High-Side | Digi-Key | |
| Gate Type | GaN FET, MOSFET (N-Channel) | Digi-Key | |
| High Side Voltage Max Bootstrap | 200 V | Digi-Key | |
| Input Type | Non-Inverting | Digi-Key | |
| Logic Voltage Vil Vih | - | Digi-Key | |
| Mounting Type | Surface Mount | Digi-Key | |
| Number Of Drivers | 1 | Digi-Key | |
| Operating Temperature Range | -40°C ~ 125°C (TJ) | Digi-Key | |
| Package Case | 10-VFDFN Exposed Pad | Digi-Key | |
| Rise Fall Time (Typ) | 5.5ns, 5.5ns | Digi-Key | |
| Supplier Device Package | PG-VSON-10-4 | Digi-Key | |
| Voltage Supply | 4.2V ~ 11V | Digi-Key |
When To Use
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High-side GaN gate drive @ 200 V max: The 1EDN7136GXTMA1’s 200 V high-side bootstrap rating supports driving GaN or MOSFET gates on rails up to 200 V, avoiding bootstrap diode breakdown in common boost or synchronous buck topologies. Using a lower voltage driver risks bootstrap diode failure and shoot-through events during high-side switching.
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Fast switching GaN FET gate drive at 1 A peak: Its independent current source and sink capability at 1 A peak and 5.5 ns rise/fall times enable clean, low-loss switching of fast GaN devices, reducing cross-conduction and minimizing switching losses. A slower gate driver or one with insufficient peak current would cause excessive switching losses and potential thermal runaway in the GaN transistor.
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Compact surface mount designs with thermal dissipation: The 10-VFDFN exposed pad package ensures good thermal conduction in dense layouts operating up to 125°C junction temperature. Discrete or larger packages without exposed pads risk overheating and premature device failure in similarly compact high-frequency power stages.
When Not To Use
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Output currents above 1 A peak: The 1 A source/sink peak current limits gate charge drive capability for larger GaN or MOSFET gates. For loads exceeding this, use a high-current synchronous buck with external FETs to handle higher transient gate currents and maintain switching integrity.
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Switching frequencies above 500 kHz: The typical rise/fall times of 5.5 ns and bootstrap design suit moderate switching rates but may limit efficiency or distortion at ultra-high frequencies. For switching above 500 kHz, choose a high-frequency buck controller optimized for minimal gate drive delay and higher switching speed.
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Battery-powered low quiescent current systems: The device’s quiescent current is not characterized for μA-level sleep modes, making it unsuitable for ultra-low power applications. Use a low-IQ PFM buck controller instead to extend battery life in always-on sensor nodes or coin cell designs.
Application Notes
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The bootstrap voltage rating of 200 V must be rigorously observed on the high-side supply node; transient overvoltage spikes beyond this can damage the device. Ensure the bootstrap capacitor is sized for stable supply without excessive ripple.
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The switching node (SW) should be routed with minimal parasitic inductance to reduce voltage overshoot and ringing that can stress the 1EDN7136GXTMA1 gate driver output stage.
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Pins controlling the logic input (non-inverting input) must be kept free from noise coupling; use local filtering or RC debounce to prevent false switching events.
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The exposed pad must be soldered to a dedicated thermal land on the PCB with multiple vias to the ground plane for effective heat dissipation during continuous 1 A peak switching.
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Guard routing on sensitive signal traces near the gate driver output pin is recommended to minimize electromagnetic interference from the fast 5.5 ns switching edges.
Gotchas
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[Bootstrap voltage margin overlooked]: Designers often assume the bootstrap capacitor voltage will never exceed the 200 V max rating, but high switching node voltage spikes or load transients can cause overshoot beyond this threshold. This leads to bootstrap diode breakdown and erratic driver output or permanent damage. Fix by adding snubbers or clamp circuits on the bootstrap supply and verifying transient waveforms on an oscilloscope.
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[Ignoring gate drive impedance in layout]: Long or thin PCB traces to the gate driver output increase inductance, causing voltage overshoot, oscillations, and ringing on the gate node. This results in non-monotonic switching waveforms and potential device stress. Fix by placing the driver as close as possible to the gate with wide, short traces and including a small gate resistor to damp oscillations.
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[Non-inverting input noise susceptibility]: The logic input pin is non-inverting and sensitive to noise injection. Without proper filtering, switching noise can cause unintended multiple switching cycles or high-frequency chatter, seen as jitter on the output waveform. Fix by adding RC filters or ferrite beads on the logic input line and ensuring clean, well-regulated logic supply rails.
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[Startup sequencing assumptions]: Applying the logic input before the bootstrap voltage is established can result in the device failing to drive the high-side output properly, appearing as if the driver is dead or stuck in low state. This is easily missed during bench testing without proper power-up sequencing. Fix by ensuring the low-side or bootstrap supply is valid and charged before enabling the logic input signal.