Key Specs
| Spec | Value | Condition | Source |
|---|---|---|---|
| Technology | Capacitive Coupling | Digi-Key | |
| Number Of Channels | 1 | Digi-Key | |
| Voltage Isolation | 5000Vrms | Digi-Key | |
| Common Mode Transient Immunity (Min) | 100V/ns | Digi-Key | |
| Propagation Delay Tplh Tphl (Max) | 90ns, 90ns | Digi-Key | |
| Pulse Width Distortion (Max) | 20ns | Digi-Key | |
| Rise Fall Time (Typ) | 30ns, 30ns | Digi-Key | |
| Current Output High Low | 4A, 4A | Digi-Key | |
| Current Peak Output | 4A | Digi-Key | |
| Voltage Forward Vf (Typ) | - | Digi-Key | |
| Voltage Output Supply | 3V ~ 5.5V | Digi-Key | |
| Operating Temperature Range | -40°C ~ 125°C | Digi-Key | |
| Mounting Type | Surface Mount | Digi-Key | |
| Package Case | 8-SOIC (0.295”, 7.50mm Width) | Digi-Key | |
| Supplier Device Package | 8-SO | Digi-Key | |
| Approval Agency | UL | Digi-Key |
When To Use
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Isolated gate drive for 600V half-bridge @ 4A peak: The 5000Vrms galvanic isolation and 4A source/sink current capability at 15.5V supply ensure robust drive of high-voltage MOSFETs or IGBTs without risk of latch-up or insulation breakdown. Using a non-isolated driver here risks shoot-through or damage from ground potential differences causing gate overvoltage stress.
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Industrial motor inverter with 100V/ns common-mode transients: The 100V/ns minimum common-mode transient immunity (CMTI) prevents false triggering from rapid switching edges typical in motor drives. Without this, the driver could suffer erratic switching or latch-up due to noise coupling, leading to system instability or device destruction.
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Surface-mount isolated driver in 8-SOIC package for space-constrained boards: The compact 8-SOIC package (7.5mm width) combined with a 120°C/W thermal resistance allows tight PCB layouts without excessive derating or thermal issues. Larger or non-SMT isolated modules would not fit or cause excessive board space and thermal challenges.
When Not To Use
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Output current demand > 4A continuous: The maximum driver current is 4A peak; continuous currents above this risk thermal runaway and device failure. Use a high-current synchronous buck with external FETs designed for higher current handling instead.
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Quiescent current critical applications (μA sleep modes): Typical quiescent currents exceed 1.3mA and standby current is ~550µA, which drains small batteries quickly. Use a low-IQ PFM buck for long battery life in ultra-low-power designs.
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Switching frequency requirement > 500kHz: The maximum switching frequency is 1MHz but with 75ns propagation delays and 30ns rise/fall times, performance degrades significantly at very high frequency, risking timing jitter and inefficient switching. Use a high-frequency buck controller optimized for >500kHz operation.
Application Notes
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Place 100nF ceramic capacitors as close as possible to both VDD (pin 2) and VH (pin 7) supply pins to minimize supply noise and improve transient response. Follow with 1µF–10µF bulk ceramic caps nearby.
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Keep the PCB traces connecting VH and GNDISO (pin 7 and pin 8) short and wide, with multiple vias to internal ground/power planes to ensure low impedance return paths and reduce EMI coupling across the isolation barrier.
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Avoid routing any conductive areas or traces below the driver IC body to prevent capacitive coupling that degrades common-mode transient immunity.
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Filtering capacitors (100nF) should be placed close to logic input pins (IN+, IN-) to suppress switching noise and prevent false triggering.
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The propagation delay and pulse width distortion require careful timing margin analysis when cascading this driver with other stages; glitches shorter than 20ns may be filtered out by the internal deglitch circuit.
Pin numbers are package-specific. Verify against the datasheet pinout diagram before routing.
Gotchas
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[Neglecting power derating with ambient temperature]: The typical thermal resistance junction-to-ambient is 120°C/W, so at high ambient temps near 125°C, continuous 4A output current can cause junction overheating and eventual device failure despite nominal current specs. Symptom: gradual increase in junction temperature leading to thermal runaway and possible isolation barrier damage. Fix: Use thermal derating curves and ensure adequate PCB copper area and cooling.
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[Insufficient PCB via count on VH/GNDISO pins]: Routing VH and GNDISO through a single or too few vias increases loop inductance and degrades transient immunity, causing erratic switching or ringing at the gate output. Symptom: noisy gate drive waveform with overshoot on scope, intermittent switching failures. Fix: Use multiple, adequately sized vias placed close to IC pins as per layout guidelines.
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[Assuming logic input thresholds are fixed voltages]: The logic input thresholds scale with VDD (0.29–0.37·VDD low, 0.62–0.7·VDD high). Applying fixed 3.3V or 5V inputs without verifying VDD level can cause improper switching or stuck outputs. Symptom: driver output stuck ON or OFF despite input toggling. Fix: Confirm input signal levels are compatible with actual VDD during operation.
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[Using minimum pulse width near pulse width distortion limit]: The device’s pulse width distortion max is 20ns; pulses narrower than ~100ns typical output pulse width plus distortion may be clipped or misinterpreted. Symptom: missing or shortened gate pulses on scope leading to incomplete MOSFET turn-on. Fix: Ensure input pulse widths exceed minimum effective width (~120ns) after accounting for propagation delay and distortion.