Key Specs

SpecValueConditionSource
Current Continuous Drain ID 25 C107A (Tc)Digi-Key
Drain-source Voltage (Max)650 VDigi-Key
Drive Voltage Max RDS On Min RDS On15V, 18VDigi-Key
FET Feature-Digi-Key
FET TypeN-ChannelDigi-Key
Gate Charge Qg Max VGS57 nC @ 18 VDigi-Key
Gate-source Voltage (Max)+23V, -7VDigi-Key
Grade-Digi-Key
Input Capacitance Ciss Max VDS2038 pF @ 400 VDigi-Key
Mounting TypeSurface MountDigi-Key
Operating Temperature Range-55°C ~ 175°C (TJ)Digi-Key
Package Case16-PowerSOP ModuleDigi-Key
Power Dissipation (Max)454W (Tc)Digi-Key
Qualification-Digi-Key
RDS On Max ID VGS24mOhm @ 46.9A, 18VDigi-Key
Supplier Device PackagePG-HDSOP-16-6Digi-Key
TechnologySiCFET (Silicon Carbide)Digi-Key
VGS Th Max ID5.6V @ 9.5mADigi-Key

When To Use

  1. 650 V bus → 100 A DC motor drive: The 650 V max drain-source rating combined with a 107 A continuous drain current at Tc makes this part ideal for high-voltage, high-current motor drives where Si devices would struggle with avalanche or thermal runaway. Using a MOSFET with lower voltage rating risks destructive avalanche breakdown under motor back-EMF spikes.

  2. Hard-switching boost converter, 400 V output @ 50 A: The SiC technology and low gate charge of 57 nC at 18 V enable fast switching with reduced switching losses. A silicon MOSFET with higher gate charge would suffer excessive shoot-through losses and thermal stress at these power levels, leading to premature failure.

  3. High-temperature industrial inverter stage, 175°C TJ max: The 16-PowerSOP package rated to 175°C junction temperature supports operation in harsh thermal environments without derating. A standard silicon MOSFET rated only to ~150°C TJ would face accelerated parameter drift or latch-up at these temperatures.

When Not To Use

  1. Output current > 107 A continuous: The continuous drain current rating of 107 A at Tc is a hard limit. For loads exceeding this, use a multi-phase buck controller or a high-current synchronous buck with external FETs to distribute current and maintain safe junction temperatures.

  2. Battery-powered, ultra-low standby power device: Gate charge and input capacitance are relatively high (57 nC, 2038 pF), causing increased gate drive losses and quiescent current. For μA-level sleep currents use a low-IQ PFM buck instead.

  3. Switching frequency above 500 kHz for miniature magnetics: The gate charge and input capacitance limit switching speed and increase losses at high frequencies. Use a high-frequency buck controller optimized for low gate charge and gate resistance instead.

Application Notes

  1. The switching node (SW) is a high dV/dt node; keep SW loop area minimal to reduce EMI and ringing. Use wide, low-inductance copper for SW and source return paths.

  2. Pins 3 and the gate and source pin are sensitive to noise injection; route gate drive traces away from SW node and use low-inductance gate resistors to prevent parasitic turn-on.

  3. The module’s 16-PowerSOP package has multiple source pins; connect all source pins to a low-impedance ground plane to ensure uniform current sharing and minimize thermal gradients.

  4. Guard routing around the gate driver pins is recommended to reduce capacitive coupling from the switching node and avoid false gating or oscillations.

  5. The maximum gate-source voltage is +23 V / -7 V, so gate drivers must be designed with clamps or regulated supplies to avoid overvoltage stress during transient conditions.

Gotchas

  1. [Underestimating TJ at high switching frequency]: Designers may assume the 454 W max power dissipation at Tc applies directly at high switching frequencies, ignoring increased switching losses and thermal impedance at pulse durations. Result: device junction overheats despite average power within limits, causing intermittent thermal shutdown or parameter shift. Fix: Perform transient thermal simulations including switching loss profiles and measure TJ with IR thermography or junction temperature sensors.

  2. [Gate drive ringing due to high input capacitance]: The large input capacitance (2038 pF at 400 V) combined with fast gate drivers can cause high-frequency oscillations on the gate node if layout parasitic inductance is not minimized. Symptom: oscillatory gate voltage waveform, increased EMI, and potential device shoot-through. Fix: add small gate resistors (5–10 Ω), optimize gate drive loop inductance, and use Kelvin source connections.

  3. [False turn-on from negative gate voltage transients]: The -7 V maximum gate-source rating is often overlooked; negative voltage spikes from switching node ringing can exceed this limit, causing gate oxide stress or permanent damage. Symptom: sudden increase in leakage or device failure after switching transient. Fix: include negative voltage clamps or diode clamps on the gate drive line and verify gate voltage waveforms on scope.

  4. [Insufficient source pin paralleling causes uneven heating]: Using only a subset of source pins for grounding can create hot spots due to uneven current distribution in the 16-PowerSOP package. Symptom: localized overheating, early package delamination, or bond wire lift-off observed in thermal imaging. Fix: connect all source pins with low-impedance copper to a solid ground plane and check current density with thermal camera during prototype testing.