Key Specs
| Spec | Value | Condition | Source |
|---|---|---|---|
| Current Continuous Drain ID 25 C | 100A (Tc) | Digi-Key | |
| Drain-source Voltage (Max) | 1200 V | Digi-Key | |
| Drive Voltage Max RDS On Min RDS On | 15V | Digi-Key | |
| FET Feature | - | Digi-Key | |
| FET Type | N-Channel | Digi-Key | |
| Gate Charge Qg Max VGS | 162 nC @ 15 V | Digi-Key | |
| Gate-source Voltage (Max) | +15V, -4V | Digi-Key | |
| Grade | - | Digi-Key | |
| Input Capacitance Ciss Max VDS | 4818 pF @ 1000 V | Digi-Key | |
| Mounting Type | Through Hole | Digi-Key | |
| Operating Temperature Range | -40°C ~ 175°C (TJ) | Digi-Key | |
| Package Case | TO-247-4 | Digi-Key | |
| Power Dissipation (Max) | 469W (Tc) | Digi-Key | |
| Qualification | - | Digi-Key | |
| RDS On Max ID VGS | 28.8mOhm @ 50A, 15V | Digi-Key | |
| Supplier Device Package | TO-247-4L | Digi-Key | |
| Technology | SiCFET (Silicon Carbide) | Digi-Key | |
| VGS Th Max ID | 3.6V @ 17.7mA | Digi-Key |
When To Use
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1200 V industrial inverter → 100 A peak motor drive: The 1200 V maximum drain-source voltage and 100 A continuous current at 25°C make this device suitable for high-voltage, high-current SiC inverter legs. Using a MOSFET with lower voltage rating would risk avalanche breakdown during switching transients, causing device failure.
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High-frequency DC-DC conversion → 48 V to 12 V @ 50 A: The low R_DS(on) of 28.8 mΩ at 50 A with a 15 V gate drive reduces conduction losses significantly at high currents, preventing thermal runaway in demanding buck converter stages. A slower MOSFET or one with higher gate charge would increase switching losses and heat dissipation, risking thermal shutdown.
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Through-hole power stage upgrade → replacing legacy IGBTs: The SiC MOSFET’s TO-247-4 package with a 469 W maximum power dissipation at case temperature allows direct drop-in replacement to improve efficiency and switching speed in through-hole designs. Using a standard silicon MOSFET with higher gate charge or slower switching can cause excessive switching losses and shoot-through in hard-switched topologies.
When Not To Use
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Output current > 100 A continuous at 25°C: The continuous drain current rating of 100 A at 25°C limits this device under heavy loads. Use a multi-phase buck controller with parallel MOSFETs to distribute current and improve thermal management.
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Input voltage difference < 1 V for noise-sensitive analog supply: The gate-source voltage max of +15 V/-4 V and lack of low-noise linear regulation disqualify this MOSFET for tight voltage regulation with minimal noise. Use an LDO regulator instead.
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Switching frequency above 500 kHz in a compact converter: The gate charge of 162 nC at 15 V limits switching speed and increases driver losses at very high frequencies. Use a high-frequency buck controller designed for ultra-fast gate drive and low gate charge MOSFETs.
Application Notes
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The switching node (SW) connected to the MOSFET drain requires tight layout to minimize parasitic inductance; long loops increase voltage overshoot risking gate oxide stress.
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Gate drive pins (pin 1 and pin 4 in TO-247-4) should be routed with short, low-inductance traces and have a dedicated low-impedance return path to the source pin to prevent gate ringing and false turn-on.
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Negative gate-source voltage must never exceed -4 V; consider adding a gate clamp or negative bias supply during off intervals to protect the gate oxide, especially in inductive switching conditions.
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Ensure thermal vias and copper area under the package tab are maximized since the 469 W max power dissipation rating assumes ideal heat sinking at the case; poor thermal contact leads to TJ exceeding 175°C.
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Avoid routing sensitive control or signal lines near the SW node due to high dv/dt and EMI; use ground shielding or guard traces around gate driver input pins to suppress noise coupling.
Pin numbers are package-specific. Verify against the datasheet pinout diagram before routing.
Gotchas
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[Underestimating temperature derating]: The 100 A continuous current rating applies at 25°C case temperature; engineers often assume it holds at higher TJ without checking thermal derating curves, leading to thermal runaway as R_DS(on) increases with temperature. Fix: measure actual case temperature under load and derate current accordingly using provided TJ vs. R_DS(on) graphs.
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[Gate driver overshoot causing gate oxide stress]: Because the maximum gate-source voltage is +15 V and -4 V, transient overshoot from fast switching or ringing can exceed these limits unnoticed on a scope with insufficient bandwidth, causing premature gate oxide degradation. Fix: implement RC snubbers or dedicated gate clamps and verify gate voltage with high-bandwidth probes.
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[Incorrect SW node layout causing voltage spikes]: A layout with excessive parasitic inductance on the drain or source return path can cause large voltage overshoot and oscillations during switching, triggering false turn-on or device latch-up. Fix: minimize loop area, use Kelvin source connections if possible, and verify switching waveforms on the SW node.
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[Startup with no minimum load causing erratic switching]: In hard-switching topologies using this MOSFET, removing the minimum load can cause the converter to enter unstable switching or oscillations due to low conduction current and gate drive thresholds near V_GS(th). Fix: ensure a minimum load or add gate drive bias margin to maintain stable conduction region during startup.