Key Specs
| Spec | Value | Condition | Source |
|---|---|---|---|
| Current Continuous Drain ID 25 C | 103A (Tc) | Digi-Key | |
| Drain-source Voltage (Max) | 750 V | Digi-Key | |
| Drive Voltage Max RDS On Min RDS On | 15V, 20V | Digi-Key | |
| FET Feature | - | Digi-Key | |
| FET Type | N-Channel | Digi-Key | |
| Gate Charge Qg Max VGS | 74 nC @ 18 V | Digi-Key | |
| Gate-source Voltage (Max) | +23V, -7V | Digi-Key | |
| Grade | Automotive | Digi-Key | |
| Input Capacitance Ciss Max VDS | 2577 pF @ 500 V | Digi-Key | |
| Mounting Type | Surface Mount | Digi-Key | |
| Operating Temperature Range | -55°C ~ 175°C (TJ) | Digi-Key | |
| Package Case | 22-PowerBSOP Module | Digi-Key | |
| Power Dissipation (Max) | 394W (Tc) | Digi-Key | |
| Qualification | AEC-Q101 | Digi-Key | |
| RDS On Max ID VGS | 14mOhm @ 55.8A, 20V | Digi-Key | |
| Supplier Device Package | PG-HDSOP-22 | Digi-Key | |
| Technology | SiCFET (Silicon Carbide) | Digi-Key | |
| VGS Th Max ID | 5.6V @ 12.3mA | Digi-Key |
When To Use
-
750 V industrial motor drive @ 80 A: The 750 V drain-source voltage rating combined with a continuous drain current of 103 A (Tc) ensures the MOSFET can handle the high voltage and current stress typical of industrial motor inverters. A lower-voltage MOSFET or a silicon device would risk avalanche breakdown or thermal runaway under transient load conditions.
-
Automotive DC-DC converter 400 V → 48 V @ 50 A: The 14 mΩ Rds(on) at 55.8 A and 20 V gate drive minimizes conduction losses, critical for automotive systems where efficiency and heat dissipation are tightly constrained. Using a generic silicon MOSFET with higher Rds(on) would cause excessive junction temperature rise leading to premature device failure.
-
High-frequency resonant converter switching at 200 kHz, 90 A peak: The SiC FET technology with a maximum gate charge of 74 nC at 18 V enables faster switching and reduced gate losses compared to silicon devices, maintaining manageable switching losses at high current. A standard MOSFET without SiC technology would experience excessive switching loss and potential thermal runaway.
When Not To Use
-
Output current above 103 A continuous: The continuous drain current at 25°C is limited to 103 A (Tc), so this device cannot safely deliver higher currents. Use a multi-phase buck controller to distribute current load across multiple FETs and avoid device overstress.
-
Quiescent current critical applications (e.g., battery-powered sensor node): The datasheet does not specify ultra-low gate leakage or quiescent current optimized for μA sleep modes. Use a low-IQ PFM buck for applications where standby power dominates system life.
-
Switching frequency above 500 kHz required: Although the gate charge is moderate, the high gate charge at 74 nC limits switching frequency efficiency gains beyond 500 kHz. Use a high-frequency buck controller designed for lower gate charge FETs to reduce switching losses and EMI at very high frequencies.
Application Notes
-
The switching node (SW) must be laid out with minimal parasitic inductance to prevent voltage overshoot spikes exceeding the 750 V rating during fast turn-off transitions. Use a compact copper pour and multiple vias directly under the device.
-
Pins 3 and the gate and source pin are noise-sensitive and require a dedicated low-inductance gate drive loop. Place the gate resistor close to pin 3 and route the source return with a wide copper area to minimize switching ringing.
-
Guard routing around the device is recommended on high-voltage pins to prevent corona discharge at elevated temperatures near 175°C junction temperature.
-
The negative gate-source voltage rating (-7 V max) must be strictly observed to avoid gate oxide degradation; a gate driver with a dedicated negative clamp or a bootstrap diode is recommended.
-
The input capacitance (Ciss max 2577 pF @ 500 V) affects the resonant frequency of the gate drive loop; gate drive circuitry should be designed to handle this capacitance to avoid slow switching edges and increased EMI.
Pin numbers are package-specific. Verify against the datasheet pinout diagram before routing.
Gotchas
-
[Underestimating gate drive voltage margin]: Designers often assume a 15 V gate drive is sufficient since Rds(on) is specified at 20 V, but the threshold voltage max is 5.6 V at 12.3 mA. Operating at 15 V gate drive increases Rds(on) and switching losses significantly, causing unexpected efficiency drop and thermal stress.
Fix: Use a 20 V gate drive supply to ensure minimal Rds(on) and stable switching performance, verifying with gate voltage measurement during switching. -
[Ignoring negative gate voltage limit during turn-off]: During hard switching or inductive load commutation, the gate can undershoot below -7 V due to inductive ringing, causing permanent gate oxide damage. This manifests as progressive threshold voltage shift and eventual device failure.
Fix: Add a gate drive clamp or a Schottky diode to limit negative swing; verify gate-source voltage waveform with high-bandwidth probe. -
[Layout-induced oscillations due to high input capacitance]: The large input capacitance (2577 pF) combined with long gate drive traces can create LC oscillations, causing erratic switching, increased EMI, and false triggering of protection circuits.
Fix: Minimize gate loop area, use a small gate resistor (e.g., 1–5 Ω), and decouple the gate driver power supply closely. -
[Thermal runaway at high junction temperatures near 175°C TJ limit]: Although rated to 175°C junction temperature, the Rds(on) increases exponentially with temperature; designers assuming constant Rds(on) risk thermal runaway in continuous high-current operation.
Fix: Use thermal derating curves to size heatsinking, monitor junction temperature in testing, and design for maximum continuous current below the 103 A rating at 25°C case temperature.