Key Specs
| Spec | Value | Condition | Source |
|---|---|---|---|
| Current Continuous Drain ID 25 C | 3A (Ta) | Digi-Key | |
| Drain-source Voltage (Max) | 60 V | Digi-Key | |
| Drive Voltage Max RDS On Min RDS On | 4.5V, 10V | Digi-Key | |
| FET Feature | - | Digi-Key | |
| FET Type | P-Channel | Digi-Key | |
| Gate Charge Qg Max VGS | 24 nC @ 10 V | Digi-Key | |
| Gate-source Voltage (Max) | ±20V | Digi-Key | |
| Grade | - | Digi-Key | |
| Input Capacitance Ciss Max VDS | 759 pF @ 30 V | Digi-Key | |
| Mounting Type | Surface Mount | Digi-Key | |
| Operating Temperature Range | -55°C ~ 150°C (TJ) | Digi-Key | |
| Package Case | SOT-23-6 Thin, TSOT-23-6 | Digi-Key | |
| Power Dissipation (Max) | 1.6W (Ta) | Digi-Key | |
| Qualification | - | Digi-Key | |
| RDS On Max ID VGS | 105mOhm @ 3A, 10V | Digi-Key | |
| Supplier Device Package | SuperSOT™-6 | Digi-Key | |
| Technology | MOSFET (Metal Oxide) | Digi-Key | |
| VGS Th Max ID | 3V @ 250µA | Digi-Key |
When To Use
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3.3V or 5V low-side high-side switch @ 3A max: The 60 V drain-source voltage and 3A continuous drain current ratings of the FDC5614P allow direct switching of typical 12V or 24V rails with some margin, while its 105mΩ RDS(on) at 10V gate drive keeps conduction losses manageable. Using a device with lower voltage rating risks avalanche breakdown during load dump or inductive spikes, causing catastrophic failure.
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Reverse polarity protection for 12V automotive loads: The P-channel MOSFET simplifies ideal diode ORing with a low gate charge of 24 nC at 10 V, minimizing switching losses and voltage drop. A synchronous buck controller or N-channel MOSFET in low-side would fail this application due to more complex drive and higher conduction losses, increasing shoot-through risk or excessive heat.
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Battery-powered power path switch in handheld device: The ±20 V gate-source voltage rating and low input capacitance (759 pF at 30 V) enable robust gate drive from low-voltage controllers, reducing switching noise and improving EMI margins. Using a MOSFET with a higher gate charge or lower gate voltage rating could cause gate oxide stress or inefficient switching, pushing the device into thermal runaway during continuous load.
When Not To Use
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Output current > 3A continuous: The 3A continuous drain current rating limits maximum load capability. For currents beyond this, use a high-current synchronous buck with external FETs which can handle higher currents with better thermal management and efficiency.
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Switching frequency > 500kHz: The gate charge of 24 nC combined with the input capacitance will cause excessive switching losses and gate driver stress at very high frequencies. Use a high-frequency buck controller designed for low gate charge MOSFETs and optimized driver timing.
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Input voltage within 1V of output voltage in linear regulation: The relatively high RDS(on) and lack of linear dropout characteristics make this unsuitable for low dropout linear applications. Use an LDO regulator instead to maintain voltage accuracy and low noise in small differential voltage conditions.
Application Notes
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The SW node (drain pin) switching transitions can induce voltage spikes; keep the drain-source loop area minimal and place the FDC5614P as close as possible to the load to reduce EMI and ringing.
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Pins 3 and the gate and source pin are noise-sensitive; guard routing or ground shielding around the gate trace helps prevent false turn-on or oscillations, especially in noisy environments.
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The maximum gate-source voltage of ±20 V must never be exceeded; include a gate resistor or clamping diode if the driver can source higher voltages or during transient switching events to avoid gate oxide damage.
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The SuperSOT™-6 package has limited thermal dissipation (1.6W max at ambient); ensure PCB copper area and thermal vias are sized appropriately to maintain junction temperature within -55°C to 150°C.
Gotchas
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[Gate drive overshoot beyond ±20 V]: It’s common to assume any 10 V logic-level driver is safe, but ringing or bootstrap overshoot can push gate voltage beyond ±20 V, degrading the gate oxide and causing device failure over time. Use a low-inductance gate resistor and clamp diode to limit gate voltage excursions; verify with high-bandwidth oscilloscope probing.
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[High input capacitance causing slow switching in high-speed PWM]: The 759 pF input capacitance at 30 V combined with a modest gate drive current can slow switching edges, increasing switching losses and heating unexpectedly. Measure gate waveform rise/fall times and optimize gate driver strength or add a small gate resistor to balance switching speed and EMI.
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[Thermal runaway due to underestimated power dissipation]: Designers may use the 1.6W max power dissipation rating at ambient without factoring in PCB thermal resistance or load cycles, leading to junction temperature exceeding 150°C during continuous operation. Perform thermal simulation including PCB copper and ambient conditions, and derate current accordingly.
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[False switching from noisy gate drive traces]: Routing the gate pin trace near high di/dt nodes (SW or drain) without shielding can induce gate voltage spikes, causing intermittent switching or shoot-through in half-bridge configurations. Use guard traces tied to ground and minimize gate loop area to prevent erratic behavior on startup or transient load changes.