Key Specs
| Spec | Value | Condition | Source |
|---|---|---|---|
| Driven Configuration | High-Side, Low-Side | Digi-Key | |
| Channel Type | Independent | Digi-Key | |
| Number Of Drivers | 2 | Digi-Key | |
| Gate Type | IGBT, SiC MOSFET | Digi-Key | |
| Voltage Supply | 4.5V ~ 5.5V, 15V ~ 30V | Digi-Key | |
| Logic Voltage Vil Vih | - | Digi-Key | |
| Current Peak Output Source Sink | 10A, 10A | Digi-Key | |
| Input Type | Non-Inverting | Digi-Key | |
| Rise Fall Time (Typ) | 500ns, 33ns | Digi-Key | |
| Operating Temperature Range | -40°C ~ 110°C (TA) | Digi-Key | |
| Grade | - | Digi-Key | |
| Qualification | - | Digi-Key | |
| Mounting Type | Surface Mount | Digi-Key | |
| Package Case | 16-SOIC (0.295”, 7.50mm Width) | Digi-Key | |
| Supplier Device Package | 16-SOIC | Digi-Key |
When To Use
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High-side and low-side IGBT/SiC MOSFET gate drive, 15–30 V, 10 A peak: The dual independent drivers with 10 A peak sourcing and sinking current and a 15 to 30 V output supply voltage make this part ideal for driving high-power IGBTs or SiC MOSFETs in half-bridge topologies. Using a generic low-current driver here risks slow switching transitions, which cause excessive switching losses and can lead to thermal runaway in the power devices.
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Isolated gate driving with high common-mode transients, 1500 V, 100 kV/μs: The device’s 1500 V isolation rating combined with 100 kV/μs common-mode transient immunity allows reliable operation in noisy industrial environments. Drivers lacking sufficient isolation or transient immunity can experience latch-up or false triggering, causing shoot-through or damaging voltage spikes.
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Applications requiring dual independent outputs with fast switching edges (~33 ns fall time): When separate control of high- and low-side transistors is necessary, and fast edges are critical for minimizing switching losses, this device’s typical 33 ns fall times and 500 ns rise times are suitable. Using a driver with slower transitions in these conditions can cause excessive switching losses, increased EMI, and possible device overheating.
When Not To Use
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Output current demand above 10 A peak: The maximum peak output current is 10 A, which disqualifies this device for applications requiring higher peak currents. Use a high-current synchronous buck with external FETs instead to handle larger currents without damage.
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Switching frequency requirements above 500 kHz: This device is optimized for typical switching frequencies well below 500 kHz. For switching frequencies exceeding this, where inductor size and switching losses must be minimized, a high-frequency buck controller is more appropriate.
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Low quiescent current for battery-powered, always-on devices: The input current is typically around 8 mA, which is too high for low-power or battery-operated systems where μA-level quiescent current is critical. Use a low-IQ PFM buck controller category to avoid battery drain during standby.
Application Notes
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The dual independent outputs require careful gate resistor selection around the typical 2.2 Ω value to control switching times and avoid ringing; excessive gate resistance will slow transitions, while too low can cause EMI and device stress.
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Pins connected to the input LED diode are noise-sensitive; ensure these input traces are routed away from high-voltage or high di/dt loops to prevent false triggering.
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The 16-SOIC package footprint mandates a creepage distance of 8.3 mm between input and output to maintain isolation integrity; PCB layout must respect this spacing and avoid contamination paths.
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Use a low-inductance ground plane and place the ACPL-355JC-000E close to the power transistor gates; long gate traces add inductance, causing overshoot and oscillations.
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The internal Miller clamp activates at about 2 V to clamp parasitic gate currents during the off cycle; layout must minimize stray capacitances to prevent unintended clamp triggering that distorts gate signals.
Gotchas
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[Gate drive overshoot due to insufficient gate resistor]: Designers may assume minimal gate resistance to maximize switching speed, but without the recommended ~2.2 Ω resistor, parasitic inductance causes voltage overshoot and ringing at the gate, leading to premature device stress and EMI issues. Use a gate resistor in the 2.1 Ω to 2.2 Ω range and verify gate voltage waveforms with an oscilloscope.
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[Faulty operation from input/output signal coupling]: If input LED traces run parallel and close to the output driver traces, capacitive coupling can cause false turn-on or erratic switching of the output, appearing as jitter or partial conduction. Keep input and output lines physically separated and shielded.
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[Incorrect startup due to undervoltage lockout (UVLO) sequencing]: The internal UVLO has a threshold around 12.2 V with typical delays; if the output supply voltage ramps too slowly or out of sequence relative to input LED drive, the device may fail to start or latch in fault mode. Confirm power-up sequencing and measure UVLO delay times during bench testing.
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[Overcurrent detection misfires with low load capacitance]: The internal overcurrent sensing relies on a certain minimum load capacitance (≥ 2 nF). Using smaller capacitors or overly low gate charge MOSFETs can cause spurious OC faults, prematurely muting the output. Verify gate drive capacitive load and OC trip behavior under real load conditions before finalizing the design.