UCC28180D

Key Specs

No verified spec values available.

When To Use

1. 230 VAC → 400 V @ 360 W PFC boost: The integrated 15.2 V gate drive voltage and 2 A peak gate drive current ensure robust driving of the boost MOSFET at switching frequencies up to 250 kHz, enabling efficient power factor correction at typical mains voltages. Using a generic PWM controller without this drive capability risks MOSFET shoot-through or insufficient switching speed, causing excessive losses and possible thermal runaway.

2. Continuous conduction mode PFC at 65 kHz: The adjustable switching frequency range from 18 kHz to 250 kHz, combined with a typical minimum off-time of 570 ns, allows stable operation in continuous conduction mode over a wide frequency band. Controllers lacking this frequency flexibility or minimum off-time guarantee can suffer from subharmonic oscillation or duty cycle runaway, leading to latch-up or output voltage instability.

3. Low standby power PFC pre-regulator: The device’s maximum standby current below 3.47 mA supports low power consumption during no or light load conditions. Alternatives with higher quiescent current may cause excessive power dissipation and thermal stress in standby, degrading system efficiency and potentially causing thermal shutdown.

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When Not To Use

1. Output current > 100 mA continuous: The 100 mA maximum output current rating is insufficient for high current applications. Use a high-current synchronous buck with external FETs controller instead to handle higher load currents with adequate gate drive and thermal margin.

2. Switching frequency > 500 kHz for miniaturized inductors: The maximum switching frequency of 250 kHz limits designs requiring very high frequency for inductor size reduction. Use a high-frequency buck controller in that case.

3. Battery-powered system with ultra-low sleep current: The typical standby current of up to 3.47 mA is too high for ultra-low power battery applications where quiescent current dominates. Use a low-IQ PFM buck controller to achieve μA-level sleep currents.

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Application Notes

• Switching Node: The switching node connected to the MOSFET drain is the primary switching node and must have the smallest possible loop area to minimize parasitic inductance and EMI. Careful PCB layout with short, wide traces at this node is critical.

• Noise-Sensitive Pins: The ISENSE and VCOMP pins are noise-sensitive and must be routed away from high-current switching nodes. Proper filtering and shielding are recommended to avoid false triggering of current limit or loop compensation circuits.

• Thermal Management: Although the UCC28180D has a maximum junction temperature of 150 °C, a heatsink or adequate PCB copper area is required to maintain the junction temperature below 125 °C during typical operation, especially at switching frequencies up to 250 kHz and output currents up to 100 mA. Proper thermal design ensures reliability and prevents thermal shutdown.

• Bootstrap Circuit: Ensure the bootstrap diode and capacitor are correctly sized and placed close to the device to maintain the typical gate drive voltage of 15.2 V. Insufficient bootstrap voltage can lead to incomplete MOSFET enhancement and increased conduction losses.

• Input and Output Filtering: Use recommended input and output capacitors to minimize voltage ripple and improve transient response. Input capacitors should handle high-frequency ripple currents, while output capacitors must support ripple currents up to 1.848 A.

• Current Sensing: The sense resistor must be selected with precision and placed close to the ISENSE pin to ensure accurate current limit protection. Incorrect sensing can cause either nuisance shutdowns or device damage.

• Loop Compensation: Follow recommended compensation component values (4 kΩ resistor, 4.7 µF capacitor) to maintain loop stability

Gotchas

1. [Incorrect off-time assumption]: Assuming the minimum off-time is negligible can cause the controller to attempt duty cycles near 100%, especially at light load. This leads to subharmonic oscillations or false triggering of open-loop protection, causing output voltage instability or unexpected standby mode entry.
   Fix: Verify minimum off-time (~570 ns typical) in timing measurements and design for max duty cycle below 96%.

2. [ISENSE pin noise coupling]: Routing the ISENSE pin trace near the switching node or high di/dt loops can inject noise spikes seen as false overcurrent events, causing premature current limit or shutdown.
   Fix: Use a short, shielded trace with a local ground return and add RC filtering if noise persists.

3. [Startup bias below UVLO]: Applying VCC below the 11.5 V UVLO threshold leads to the device entering standby mode with VCOMP pulled low, which can be misinterpreted as a device failure or dead IC during bring-up.
   Fix: Ensure the bias supply ramps above 11.5 V before enabling load or switching.

4. [Output capacitor ESR and loop stability]: Using output capacitors with very low ESR can cause loop instability due to reduced phase margin, resulting in oscillations or output voltage ripple beyond ±5%.
   Fix: Choose output capacitors with moderate ESR or add small series resistance to stabilize the control loop.