Key Specs
No verified spec values available.
When To Use
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12V automotive auxiliary power @ 2A: The absolute max input voltage of 28 V with a typical start-up current under 1 mA suits standard automotive 12V rails with transient spikes. Using a synchronous buck controller here risks latch-up or shoot-through if the input voltage exceeds the IC rating during load dump events.
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Offline 110 kHz flyback converter @ 12 V, 1.5 A: The fixed switching frequency of 110 kHz and integrated PWM with 1-A peak output current enable stable operation with slope compensation, preventing subharmonic oscillation. A low-IQ PFM buck would fail here by causing unstable PWM switching and increased output ripple.
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Industrial 12 V power rail with wide temperature range (-40 to 125°C): The operating temperature and junction limits ensure reliable control in harsh environments. An LDO regulator cannot handle the required switching frequency or load current efficiently and would overheat or enter thermal shutdown.
When Not To Use
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Battery-powered sensor node with μA sleep current: The typical supply current of 11 mA disqualifies this part for ultra-low power applications. Use a low-IQ PFM buck instead to maximize battery life.
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High-current server CPU core rail > 10 A: The max output current of 2 A is insufficient for high load demands. A multi-phase buck controller is required for current sharing and thermal management.
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High-frequency DC-DC conversion above 500 kHz: The max switching frequency is 500 kHz; designs requiring smaller magnetics or faster transient response at >500 kHz need a high-frequency buck controller.
Application Notes
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The switching node (SW) pin must be routed with minimal inductance and wide traces to handle 1-A peak currents and reduce voltage overshoot. Keep the SW loop area as small as possible.
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Pins 2 and the Vref and Vfb pin are noise-sensitive inputs; place the 0.1-µF Vref bypass capacitor as close as possible to pin 2 to minimize output noise and improve reference stability.
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Implement a clean ground plane with separate analog and power grounds tied at a single point near the device to avoid ground noise coupling into the error amplifier.
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Use a 10× gate capacitance value bypass capacitor on the supply pin to stabilize gate drive transitions and prevent erratic switching.
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Avoid routing sensitive feedback traces near the switching node or high di/dt loops to reduce EMI-induced jitter and improve loop stability.
Pin numbers are package-specific. Verify against the datasheet pinout diagram before routing.
Gotchas
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[Vref bypass capacitor missing or undersized]: The datasheet specifies a strict 0.1-µF bypass capacitor on the Vref pin. Omitting or using a significantly different value leads to output voltage instability and increased noise, observable as jitter or ripple on the output voltage. Fix by placing a 0.1-µF ceramic capacitor directly at the Vref pin.
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[Start-up resistor too high]: Using a start-up resistor above the 100 kΩ max slows the VCC ramp, causing UVLO to fail or the device never to start switching. This results in a dead output or intermittent start-up. Measure the resistor value and keep it at or below 100 kΩ.
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[ESR of output capacitor too low]: The loop compensation relies on a certain ESR (around 43 mΩ typical). Using ultra-low ESR capacitors can cause loop instability or subharmonic oscillations, seen as output voltage ringing or oscillations under load. Add a small series resistor or select capacitors with appropriate ESR.
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[Incorrect timing capacitor value]: Using a timing capacitor outside the 1–100 nF range or significantly off 1 nF typical causes oscillator frequency drift or failure, leading to erratic PWM switching frequency and improper duty cycle. Verify timing capacitor value and tolerance carefully during assembly.