Key Specs
No verified spec values available.
When To Use
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Universal mains input → 250W flyback output: The TEA1755T/1,518 supports up to 250W with its integrated DCM/QR flyback and PFC controllers, including adjustable overcurrent and overvoltage protection, making it ideal for mains-powered offline supplies. Using a synchronous buck controller here risks shoot-through and insufficient input voltage rating for universal mains, causing device latch-up or destruction.
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High-efficiency standby mode in offline power supplies: Its burst mode operation with exit threshold at 2.8V and switching frequency around 36.5kHz ensures low quiescent current (12 μA bias) and minimal switching losses at light load. Alternatives like high-current synchronous buck controllers typically lack such fine burst mode control, leading to thermal runaway or excessive standby power dissipation.
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Flyback converter requiring robust demagnetization detection: Both converters incorporate continuous mode protection using demagnetization detection and power level reduction to avoid transformer saturation and overcurrent events. Using an LDO regulator or simple buck controller would not provide this; resulting in potential transformer core saturation and device destruction under abnormal load or startup conditions.
When Not To Use
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Output current demand above 250W rating: The TEA1755T/1,518 maxes out at 250W application power; for higher currents, use a multi-phase buck controller designed for load sharing and higher current capability.
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Very low quiescent current for coin cell-powered devices: With a bias current of 12 μA and soft-start currents in tens of μA, this device is not optimized for μA-level sleep modes. Use a low-IQ PFM buck for ultra-low standby power.
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Non-isolated DC-DC with input-output galvanic isolation requirement: This device is an integrated flyback and PFC controller without isolation features. For galvanic isolation, use an isolated flyback controller.
Application Notes
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The switching node (SW) must be routed with low inductance and minimal loop area to reduce EMI and ensure reliable valley switching; this also helps maintain the typical flyback switching frequency near 73kHz.
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Pins related to burst mode operation and voltage sensing (such as FBCTRL and VINSENSE) are noise sensitive; keep their traces short, shielded, and away from high-current switching paths.
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Demagnetization detection timing (~2.2 μs suppression time) relies on accurate timing of the off-time; layout parasitic capacitances or improper snubber design can cause false demag detection and premature power level reduction.
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The PFC driver pin requires careful gate drive layout to support peak currents up to 1.2A sink and 500mA source at specified voltages; undersized PCB traces or insufficient decoupling can cause oscillations or incomplete MOSFET switching.
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The FBCTRL pin timeout protection resistor (recommended 200kΩ) must be precise and low noise to avoid false fault triggering and unintended latch conditions.
Gotchas
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[Demagnetization detection timing skew]: Assuming the demagnetization suppression time of 2.2 μs is fixed regardless of layout or snubber components leads to missed or false demag events. This causes erratic switching frequency and power level throttling. Fix by measuring actual off-time waveforms with an oscilloscope and selecting snubber components and PCB routing that preserve clean magnetizing current zero-cross detection.
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[Startup bias current underestimated]: Designers expecting sub-μA startup current may be surprised by the 12 μA bias current, causing delayed startup or insufficient HV pin capacitor sizing. This manifests as extended startup times or failure to reach UVLO threshold. Fix by ensuring HV startup capacitor and HV supply ramp account for this bias current and verifying startup waveforms on bench.
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[Burst mode hysteresis voltage mismatch]: The burst mode voltage difference ranges from 325 to 455 mV, but improper feedback resistor tolerances or load variations can shift thresholds, causing unstable burst mode operation or premature exit. Symptom is output voltage ripple or audible noise at light load. Fix by using precision feedback components and validating burst mode voltage thresholds under worst-case load.
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[PFC driver gate signal timing errors]: The PFC driver has minimum and maximum driver delay times (-50 ns min, 0 ns typical, 80 ns max) and on-time variations that if ignored cause overlapping conduction or dead-time violations in the PFC MOSFET gate drive, resulting in shoot-through or excessive switching losses. Fix by measuring gate drive timing on the final PCB and adjusting gate resistors or layout to ensure clean transitions within specified timing windows.