SLG51003V Datasheet, Specs & Application Notes

Key Specs

Spec	Value	Condition	Source
Mounting Type	Surface Mount		Digi-Key
Package Case	14-UFQFN Exposed Pad		Digi-Key

1.4 V @ 475 mA LDO output for sensitive analog blocks: The ultra-low output noise of 16 µV rms and excellent PSRR of 98.5 dB at 1 kHz make this ideal for powering noise-sensitive analog or RF front-ends. A switching regulator would inject switching noise that is challenging to filter, potentially degrading signal integrity.
Powering core logic at 800 mA from 0.8 V to 1.5 V rail: The LDO_LV input range down to 0.8 V and 800 mA max output current make this part suitable for low-voltage digital cores with tight voltage accuracy (±1%). A synchronous buck controller might achieve better efficiency but risks instability and higher output ripple at these low voltages without complex compensation.
Low quiescent current always-on supply from 2.8 V to 5 V: With a quiescent current as low as 14 µA and shutdown current below 240 nA, this device suits systems requiring always-on power rails with minimal leakage. A multi-phase buck or high-frequency buck would consume significantly more quiescent current, draining battery or standby power budgets unnecessarily.

> 800 mA output current demand: The output current max of 800 mA is a hard limit; for loads exceeding this, use a high-current synchronous buck with external FETs to handle higher current with better thermal management and efficiency.
Input voltages above 6 V or wide input range: This device maxes at 6 V input; for higher voltage rails, a synchronous buck controller designed for high-voltage inputs is necessary to avoid device damage or latch-up.
Need for switching frequencies above 100 kHz: With a max switching frequency of 100 kHz, this device is not suitable for applications requiring >500 kHz to shrink inductor size or reduce EMI. Use a high-frequency buck controller in such cases.

The switching node (SW) must have a low-inductance path and be physically close to the inductor and catch diode to minimize switching noise and ringing.
Pins 4, 7, and the LDO enable inputs pin are noise-sensitive; route these with clean, short traces and avoid routing near noisy digital lines to maintain stable enable thresholds.
The exposed pad must be soldered directly to a large PCB copper area with thermal vias to keep junction temperature within limits, considering the typical junction-to-ambient thermal resistance of 55.4 °C/W.
Maintain the recommended output capacitance range (2.2 µF to 10 µF) on LDO outputs with low ESR ceramic caps to ensure stability and transient response; avoid electrolytic caps with high ESR.
Keep the CS pin trace short and shielded from digital switching noise to ensure reliable chip select detection and prevent false resets or mode changes.

[Startup current limit interaction]: Setting a startup current limit too close to the load current can cause the LDO to stall or take excessively long to reach output voltage, appearing as a “dead” regulator on scope with slow ramp or no output. Fix by verifying startup current limit is sufficiently above maximum load current and calculating startup timeout per the provided equation.
[Output capacitor ESR affecting stability]: Using output capacitors with high ESR or large electrolytics can cause oscillations or erratic output voltage ripple, despite meeting nominal capacitance specs. This manifests as ringing or unstable regulation on the scope output waveform. Fix by using low-ESR ceramic capacitors within the specified 2.2–10 µF range.
[Improper UVLO threshold setting]: Setting undervoltage lockout (UVLO) threshold too low or outside recommended 2.658 V typical results in unpredictable power-on reset behavior and potential latch-up during brown-out events. Fix by configuring UVLO thresholds per datasheet recommended values to ensure clean startup and shutdown sequencing.
[Inadequate debounce on CS pin]: Not accounting for the minimum 32 µs debounce time on the CS pin can cause multiple unintended toggles or false chip select detections, leading to erratic enable/disable cycles. Fix by adding hardware or firmware debounce logic and ensuring trace noise immunity on the CS input.