Key Specs

SpecValueConditionSource
TechnologyMagnetic CouplingDigi-Key
Number Of Channels1Digi-Key
Voltage Isolation5000VrmsDigi-Key
Common Mode Transient Immunity (Min)50kV/µs (Typ)Digi-Key
Propagation Delay Tplh Tphl (Max)305ns, 325nsDigi-Key
Pulse Width Distortion (Max)-Digi-Key
Rise Fall Time (Typ)475ns, 447nsDigi-Key
Current Output High Low7.8A, 7.3ADigi-Key
Current Peak Output8ADigi-Key
Voltage Forward Vf (Typ)-Digi-Key
Voltage Output Supply18V ~ 28VDigi-Key
Operating Temperature Range-40°C ~ 125°CDigi-Key
Mounting TypeSurface MountDigi-Key
Package Case16-PowerSOIC (0.350”, 8.89mm Width), 15 LeadsDigi-Key
Supplier Device PackageeSOP-R16BDigi-Key
Approval AgencyULDigi-Key

When To Use

When Not To Use

  1. Output current above 8 A peak: The peak gate output current max of ±8 A limits drive capability for larger MOSFETs or parallel arrays. Use a high-current synchronous buck with external FETs to handle the higher gate charge and current demands without distortion or excessive delay.

  2. Switching frequency above 150 kHz: The max switching frequency rating of 150 kHz restricts applications requiring smaller magnetics or tighter transient response. For switching frequencies exceeding 500 kHz, choose a high-frequency buck controller optimized for fast gate transitions and low propagation delay jitter.

  3. Very low output voltage differential (<1 V) with noise-sensitive loads: This part lacks low-dropout and low-noise regulation capabilities, and the logic output voltage max is 0.5 V (max) which is insufficient for linear regulation at low voltage differences. Use an LDO regulator for tightly regulated, low-noise outputs with small input-to-output voltage differentials.


Application Notes

Gotchas

  1. Incorrect Gate Resistor Connection:

    • Mistake: Connecting the gate resistor intended for turn-on to the GL pin or turn-off resistor to the GH pin.
    • Failure: This reverses the gate drive currents, causing improper switching, increased losses, and possible device damage.
    • Fix: Ensure turn-on gate resistors connect to GH pin (Pin 13) and turn-off resistors to GL pin (Pin 16) as specified.
  2. Insufficient Bootstrap Capacitor Sizing:

    • Mistake: Using a bootstrap capacitor smaller than the minimum 3 µF or omitting it entirely.
    • Failure: Leads to unstable VGXX voltage, causing erratic gate drive and potential switching failures.
    • Fix: Use at least 3 µF low-ESR capacitors between VEE and COM and between VISO and VEE as specified.
  3. Neglecting SNS Pin Filtering:

    • Mistake: Not applying an appropriate filter capacitor or miscalculating the discharge time constant on the SNS pin.
    • Failure: Results in false or missed short-circuit fault detection, risking device damage.
    • Fix: Implement the recommended filter capacitor with a discharge time constant matched to the SNS fault monitoring time (450 ns to 900 ns).