Key Specs
No verified spec values available.
When To Use
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12V automotive accessory → 9.5V @ 3A: The input voltage range up to 38 V with a startup threshold minimum of 16 V and a typical operating junction temperature to 125 °C suits automotive 12V rails with load-dump transients. A synchronous buck controller without 800 V HV pin tolerance risks latch-up or damage during transients.
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Offline auxiliary power supply → 10 V @ 5 A: The high-voltage pin rating of −0.3 to 800 V and the integrated overvoltage protection at 36.5 V make it ideal for flyback designs feeding isolated auxiliary rails. Using a low-voltage synchronous buck controller here risks shoot-through or device destruction under high-voltage spikes.
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Battery charger with input 8–38 V → regulated 9.5 V output: The tight regulation voltage range (9.5–10.6 V) and built-in current limit threshold at 0.8 V allow precise current control up to 8 A output current limit. A linear regulator would dissipate excessive heat and enter thermal shutdown, while simpler controllers lack overcurrent and OVP features needed for safe charging.
When Not To Use
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>8 A output current requirement: The output current limit is specified at 8 A max, which is insufficient for higher loads. Use a multi-phase buck controller to safely share current and reduce stress on individual devices.
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Input voltage below 8 V: The minimum operating voltage is 8.5 V, and startup threshold is at least 16 V, so it won’t reliably start or regulate below 8 V. Use a low-IQ PFM buck for efficient operation at low input voltages.
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Switching frequency > 500 kHz: The maximum switching frequency clamp is 25 kHz, far below high-frequency needs. Use a high-frequency buck controller when the design requires compact inductors or EMI advantages from higher switching frequencies.
Application Notes
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The switching node (SW) must be kept as short and low-inductance as possible to minimize voltage spikes and ringing that can exceed the 800 V HV pin rating during flyback transitions.
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Pins 3 and the ZCD and Fault pin are noise sensitive; route their traces away from the SW node and power ground to avoid false triggering or latch faults.
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The internal latch logic reset level ranges from 6.0 to 7.2 V; ensure that the VCC line is stable and clean during startup to avoid unintended latching or failure to reset.
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The blanking delay after turn-off (typical 0.7 µs) and leading-edge blanking duration (typical 125 ns) require careful timing of current sensing circuitry to avoid false current limit trips.
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The device requires a soft-start capacitor sized to achieve a 4 ms typical soft-start period; undersizing can cause output overshoot and inrush current stress.
Gotchas
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[Startup below 16 V input]: Many engineers assume the device will start at minimum operating voltage (8.5 V), but the startup threshold minimum is actually 16 V. Attempting to start below this causes the IC to remain latched off, appearing dead on power-up.
Fix: Verify input voltage ramp exceeds 16 V before enabling the device or add a pre-regulator stage. -
[ZCD pin noise coupling]: Routing the Zero Current Detection (ZCD) pin trace too close to the SW node or noisy ground loops causes erratic switching frequency and false demagnetization detection, leading to unstable output voltage or premature shutdown.
Fix: Use a dedicated quiet ground reference for ZCD and route the trace away from switching node noise. -
[External resistor tolerance on OPP setting]: The overpower protection gain depends on an external resistor Ropp; if resistor tolerance is wide or temperature drift is ignored, the OPP threshold shifts, causing either nuisance shutdowns or failure to protect against overcurrent.
Fix: Use precision resistors with low temperature coefficient and verify OPP behavior under worst-case conditions. -
[Insufficient output capacitance ESR]: The internal control loop assumes certain ESR levels to maintain stability; using ultra-low ESR capacitors (e.g., ceramic only) may cause loop instability or high-frequency oscillations not predicted by simulations.
Fix: Include a small ESR or add RC damping network in the output filter stage and validate loop stability on the bench.