DRFLYBACK-A

Key Specs

No verified spec values available.

When To Use

1. 117Vdc(83Vac)/37Vdc input → 15.2V @ 10A: The DRFLYBACK-A supports a wide input range up to 450Vdc and can handle output power up to 150W, making it ideal for moderate power offline supplies operating from universal AC mains. Using a synchronous buck controller here risks shoot-through or voltage overstress due to the high input voltage and lack of galvanic isolation.

2. Flyback converter with 1–2nF snubber capacitance → 15V output: The internal snubber capacitor rating (<2.4nF max) and ZCD target voltage window (2.2–2.5V) enable tight control of leakage energy and zero current detection without excessive losses. A synchronous buck controller would lack the native zero current detection and isolation needed, potentially causing transformer saturation and catastrophic latch-up.

3. Low standby power (<30mW) universal input adapter: Typical no-load consumption of 27–29mW suits designs targeting energy efficiency compliance at standby. Linear regulators would dissipate significantly more power at no load, causing thermal runaway or excessive battery drain in auxiliary circuits.

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When Not To Use

1. Output current > 10A continuous: The DRFLYBACK-A’s maximum output power is 150W with typical current limits around 1A sense threshold, so it’s unsuitable for high current loads. Use a multi-phase buck controller for current sharing and thermal distribution.

2. Input voltage close to output voltage (<1V differential): The device’s input brown_in_out_voltage_min is 37Vdc and output is around 15.2V, so it is not designed for low drop-out operation. Use an LDO regulator when input-output differential is small and noise sensitivity is critical.

3. Switching frequency > 500kHz required for compact magnetics: The minimum switching frequency is 89kHz but the design equations and device constraints limit high-frequency operation. Use a high-frequency buck controller for switching frequencies above 500kHz to reduce magnetics size.

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Application Notes

• The switching node connected to the DRFLYBACK-A’s high-voltage MOSFET drain is the primary switching node and must have the smallest possible loop area to minimize EMI and switching losses.
• The ISENSE pin is noise-sensitive; routing should minimize noise coupling and use proper filtering to maintain accurate current sensing and prevent false triggering of current limit.
• The device’s internal current limit sense threshold is fixed at 1A with a voltage limit of -0.20V to -0.25V at low line; ensure the sense resistor and layout maintain signal integrity for reliable operation.
• Although the device is designed for operation without a dedicated heatsink, good PCB thermal design is recommended to maintain junction temperature below the specified maximum of -150°C (typical is likely a typo and should be verified, but use as given).
• The device operates with input voltages up to 450Vdc (318Vac), so all external components connected to the input must be rated accordingly to prevent damage.
• For optimal efficiency (typical 88.91% with a max of 92.78%), minimize parasitic inductances and use low RDS(on) MOSFETs as specified (typical 1.2Ω).
• Ensure the snubber capacitance remains below 2nF to avoid excessive losses and maintain stable operation.
• The device supports a switching frequency minimum of 89kHz; switching frequency selection should be done through the laser trim voltage (~2.0V) for light load mode optimization.
• The OTP and OVP features require correct voltage thresholds and pull-up currents as specified

Gotchas

1. [Incorrect snubber capacitor sizing]: Assuming a larger snubber capacitor than the max 2.4nF allowed can cause excessive switching losses and distorted ZCD detection, leading to unstable switching frequency and output ripple. The symptom is irregular switching waveforms on SW and elevated junction temperature. Fix by measuring total snubber capacitance on the board and keeping it below 2.4nF.

2. [Floating or noisy CSN pin]: Designers may route the current sense line close to the switching node or ground it improperly, causing false triggering of the 0.5V latch mode current limit. This results in premature shutdown or intermittent operation. Fix by shielding and filtering the CSN trace, and verifying sense voltage with an oscilloscope during load transients.

3. [Startup with insufficient VDDA voltage]: The UVLO thresholds for VDDA are 6.5–8.5V off and 19–21V on; powering the device with VDDA below these levels causes the IC to remain inactive, which might be misinterpreted as a dead device during bring-up. Fix by confirming VDDA ramp timing and ensuring it exceeds 21V before enabling output load.

4. [Output capacitor ESR effects on stability]: Using output capacitors with excessively low ESR or ceramic-only capacitors without bulk electrolytics can disrupt the output undervoltage protection threshold at 0.375–0.75V, causing erratic fault detection and output oscillation. Fix by selecting output capacitors with ESR in the recommended range or adding a small bulk capacitor to stabilize the output voltage feedback loop.