Key Specs
| Spec | Value | Condition | Source |
|---|---|---|---|
| Channel Type | Independent | Digi-Key | |
| Current Peak Output Source Sink | 2.3A, 4.6A | Digi-Key | |
| Driven Configuration | Half-Bridge | Digi-Key | |
| Gate Type | IGBT, SiC MOSFET | Digi-Key | |
| Input Type | Non-Inverting | Digi-Key | |
| Logic Voltage Vil Vih | 1.1V, 1.7V | Digi-Key | |
| Mounting Type | Surface Mount | Digi-Key | |
| Number Of Drivers | 2 | Digi-Key | |
| Operating Temperature Range | -40°C ~ 125°C (TA) | Digi-Key | |
| Package Case | 16-SOIC (0.295”, 7.50mm Width) | Digi-Key | |
| Rise Fall Time (Typ) | 48ns, 48ns | Digi-Key | |
| Supplier Device Package | PG-DSO-16-U02 | Digi-Key | |
| Voltage Supply | 13V ~ 20V | Digi-Key |
When To Use
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SiC MOSFET gate drive @ 15A peak: The 2.3A peak source and 4.6A peak sink current capability deliver fast switching edges for high gate charge devices like SiC MOSFETs, minimizing switching losses and preventing excessive dv/dt stress. Using a driver with lower peak drive current risks slow turn-off, causing shoot-through and thermal runaway during hard switching.
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Half-bridge motor drive, 13–20V supply: The half-bridge configuration with a 13–20V supply range fits automotive or industrial motor drives operating from 12V nominal rails with margin. A single-ended or low-voltage driver would fail to fully enhance IGBTs or SiC MOSFETs, resulting in increased conduction losses and potential latch-up from incomplete gate drive.
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Dual independent channel gate driver with non-inverting input: When isolated dual outputs with independent logic control are needed, this driver’s independent channels and non-inverting inputs simplify PWM synchronization and dead-time control. Using a driver with only complementary outputs risks shoot-through during complementary switching or complex external logic to fix timing.
When Not To Use
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Output current > 5A peak per channel: The 2.3A source and 4.6A sink peak current limit this part to moderate gate charge devices. For higher gate charge loads requiring >5A peak, use a high-current synchronous buck with external FETs that can handle higher transient currents without excessive gate delay.
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Battery-powered sensor with μA sleep current: The driver’s quiescent current is not optimized for ultra-low-power applications, disqualifying it for μA-level sleep modes. Use a low-IQ PFM buck instead to minimize standby power draw and extend battery life.
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Switched-mode converter > 500kHz switching frequency: The 48ns rise and fall times limit switching speed and efficiency at frequencies above 500kHz, causing increased switching losses and EMI. Use a high-frequency buck controller designed for sub-20ns transitions and stable operation above 500kHz.
Application Notes
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The half-bridge switching node (SW) experiences fast dv/dt transitions; route the gate drive return and power ground planes tightly to minimize loop inductance and reduce EMI coupling into sensitive logic input pins (pin #3, #11).
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Pins controlling the input logic (non-inverting inputs) must be shielded from switching noise; add local RC filters or ferrite beads if logic glitches appear during switching transients.
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Use Kelvin-sense connections for the gate drive return to avoid erroneous switching caused by voltage drops in the power ground return path, especially when driving SiC MOSFET gates with large gate charge.
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Maintain at least 7.5mm clearance around the PG-DSO-16-U02 package to enable effective thermal conduction and allow for heat spreading on the PCB.
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Avoid running high-current traces parallel and adjacent to input pins 3 and 11 to prevent capacitive coupling of switching noise into the logic inputs, which can cause unintended switching.
Gotchas
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[Misinterpreting peak current ratings]: Assuming the 2.3A source and 4.6A sink currents can be continuously applied leads to gate driver transistor overstress and thermal runaway. The peak ratings are short-duration, not continuous currents.
What happens: Gate drive waveforms distort, switching slows, device junction temperature spikes unexpectedly.
Fix: Measure gate drive current waveforms with a high-bandwidth current probe and ensure peak currents occur only during switching transitions, not steady state. -
[Floating or noisy logic inputs]: Connecting the input pins (3 and 11) directly to noisy ground or leaving them floating can cause erratic switching or partial conduction.
What happens: Output driver toggles unpredictably, causing shoot-through or abnormal power dissipation.
Fix: Tie inputs to a clean logic rail via a pull-up or pull-down resistor, and add a small RC filter to suppress high-frequency noise. -
[Ignoring dead-time requirements in half-bridge]: Using this driver without external dead-time control can cause overlap conduction in IGBTs or SiC MOSFETs, especially at fast 48ns rise/fall times.
What happens: Shoot-through current spikes, increased EMI, and device damage during switching transitions.
Fix: Implement external dead-time insertion or use a complementary driver stage with integrated dead-time logic. -
[Undersized gate resistors causing ringing]: Using minimal or zero gate resistance to maximize switching speed can excite parasitic LC oscillations in the gate loop.
What happens: High-voltage gate ringing exceeding absolute maximum ratings, premature gate oxide stress, or false turn-on/off events.
Fix: Select gate resistors empirically to critically damp switching waveforms; verify with high-bandwidth scope probing.