Design Guides & Reference Tools
Technical reference data, industry-standard calculators, and engineering deep dives.
Power Supply Design
IPC-2221 PCB Trace Width
Required trace width for a given current and temperature rise. Based on IPC-2221B Table 6-1 empirical coefficients.
| Layer | Width (mm) | Width (mil) |
|---|---|---|
| External | -- | -- |
| Internal | -- | -- |
Buck Converter — Inductor & Output Capacitor Sizing
CCM assumption. L = (Vin − Vout) × Vout / (Vin × ΔIL × fsw). Cout,min = ΔIL / (8 × fsw × ΔVout).
| Parameter | Value |
|---|---|
| Duty Cycle D | -- |
| Inductor Lmin | -- |
| Peak Inductor Current | -- |
| Ripple Current ΔIL | -- |
| Output Cap Cout,min | -- |
MOSFET Power Loss
Hard-switched model. Pcond = Id² × Rds(on). Psw = ½ × Vds × Id × (tr + tf) × fsw. Pgate = Qg × Vgs × fsw.
| Loss Component | Power |
|---|---|
| Conduction Pcond | -- |
| Switching Psw | -- |
| Gate Drive Pgate | -- |
| Total Ptotal | -- |
Basic Circuit Analysis
Ohm's Law / Power
Enter any two known values; the remaining two are calculated. V = IR, P = IV.
RC Filter — Cutoff Frequency & Time Constant
fc = 1 / (2π R C). τ = R C. −3 dB point for both low-pass and high-pass RC filters.
| Parameter | Value |
|---|---|
| Cutoff Frequency fc | -- |
| Time Constant τ | -- |
| Attenuation @ 10× fc | -- |
| Attenuation @ 100× fc | -- |
Resistive Voltage Divider
Vout = Vin × R2 / (R1 + R2). Unloaded. Quiescent current flows from Vin through R1 + R2 to GND.
| Parameter | Value |
|---|---|
| Vout | -- |
| Divider Ratio | -- |
| Quiescent Current | -- |
Timing & Resonance
LC Resonant Frequency
f₀ = 1 / (2π √(LC)). Used for filter design, tank circuits, and resonant converter switching frequency selection.
| Parameter | Value |
|---|---|
| Resonant Frequency f₀ | -- |
| Angular Frequency ω₀ | -- |
555 Timer — Astable Mode
f = 1.44 / ((R1 + 2·R2)·C). Duty cycle = (R1 + R2) / (R1 + 2·R2). Duty cycle is always > 50% in standard astable configuration.
| Parameter | Value |
|---|---|
| Frequency | -- |
| Duty Cycle | -- |
| Period | -- |
| tHIGH | -- |
| tLOW | -- |
RF & Signal
dBm ↔ mW ↔ Vrms Converter
Enter dBm, mW, or Vrms — the others are calculated. Vrms assumes a purely resistive load at Z₀.
| Parameter | Value |
|---|---|
| Power (dBm) | -- |
| Power (mW) | -- |
| Power (W) | -- |
| Vrms into Z₀ | -- |
| Vpp (sine) | -- |
π / T Attenuator Designer
Symmetric matched attenuator (Zin = Zout = Z₀). π: two shunt resistors (R1=R3) + one series resistor (R2). T: two series (R1=R3) + one shunt (R2).
| π Network | |
|---|---|
| Component | Value |
| R1 = R3 (shunt, Ω) | -- |
| R2 (series, Ω) | -- |
| T Network | |
|---|---|
| Component | Value |
| R1 = R3 (series, Ω) | -- |
| R2 (shunt, Ω) | -- |
Analog Discrete
BJT Common-Emitter — Voltage Divider Bias
VB = VCC × R2/(R1+R2). VE = VB − 0.7 V. IC ≈ VE/RE. Stability requires R1∥R2 ≤ β·RE/10.
| Parameter | Value |
|---|---|
| VB (base) | -- |
| VE (emitter) | -- |
| IC (collector) | -- |
| VC (collector) | -- |
| VCE | -- |
| Bias stability | -- |
Zener Shunt Regulator
RS = (VS − VZ) / (IZ,min + IL,max). Designed for worst-case: minimum supply voltage, maximum load current.
| Parameter | Value |
|---|---|
| Series Resistor RS | -- |
| IZ,max (at IL=0) | -- |
| PZ,max (zener dissipation) | -- |
| PRS (resistor dissipation) | -- |
Reference Tables
Creepage & Clearance Matrix
IEC 62368-1 / 60950-1 — Pollution Degree 2, Material Group IIIb.
| Working Voltage (RMS/DC) | Clearance (mm) | Creepage (mm) |
|---|---|---|
| ≤ 50 V | 0.2 | 1.2 |
| ≤ 150 V | 1.5 | 1.6 |
| ≤ 300 V | 2.0 | 3.2 |
| ≤ 600 V | 3.2 | 6.3 |
| ≤ 1000 V | 4.2 | 10.0 |
AWG Wire Ampacity (Chassis Wiring)
NEC Table 310.15 chassis wiring. Derate 50% for bundled cables or elevated ambient.
| AWG | Ø (mm) | Max A | Ω/km |
|---|---|---|---|
| 10 | 2.588 | 55 | 3.28 |
| 12 | 2.053 | 41 | 5.21 |
| 14 | 1.628 | 32 | 8.29 |
| 16 | 1.291 | 22 | 13.2 |
| 18 | 1.024 | 16 | 20.9 |
| 20 | 0.812 | 11 | 33.3 |
| 22 | 0.644 | 7 | 52.9 |
| 24 | 0.511 | 3.5 | 84.2 |
Technical Glossary
SFDR (Spurious-Free Dynamic Range)
The ratio (dB) of the fundamental signal amplitude to the largest spurious component in the bandwidth of interest. Determines the usable dynamic range of a converter in the presence of interference.
ENOB (Effective Number of Bits)
Practical bit resolution accounting for all noise and distortion, derived from SINAD: ENOB = (SINAD − 1.76) / 6.02. A 16-bit ADC with poor layout may achieve only 12–13 ENOB.
Baud Rate vs Bit Rate
Baud rate is symbol changes per second; bit rate equals baud rate × bits-per-symbol. A 1 MBd 16-QAM link carries 4 Mbps. They are equal only for binary (1 bit/symbol) encoding.
Nyquist Frequency
The maximum representable frequency in a sampled system, equal to half the sample rate (f_s/2). Signals above this alias back into the baseband — requiring an anti-aliasing filter prior to the ADC.
Quantization Noise
The rounding error introduced when a continuous signal is mapped to a finite set of discrete levels. For a uniform N-bit ADC with a full-scale input, the theoretical SNR ≈ 6.02N + 1.76 dB.
Rds(on)
Drain-to-source resistance of a MOSFET in the fully enhanced state. Dominates conduction loss (P = I²·Rds(on)) and increases approximately proportionally to (T_J/25°C)^2.3 for Si devices.
Creepage vs Clearance
Clearance: shortest path through air between conductors — guards against flashover. Creepage: shortest path along the insulator surface — guards against tracking. Creepage ≥ Clearance always.
Reverse Recovery Time (Trr)
Time for a bipolar diode to sweep out stored minority charge after commutation from forward to reverse bias. Causes a momentary reverse current spike; negligible in Schottky and SiC diodes due to majority-carrier conduction.
ESL (Equivalent Series Inductance)
Parasitic inductance of a physical capacitor. Above the self-resonant frequency (SRF = 1/2π√(LC)), the capacitor appears inductive. MLCC packages (0402, 0201) minimize ESL for high-frequency decoupling.
Dead Time
Intentional overlap period in complementary gate drive signals during which both switches are off. Required to prevent shoot-through; minimum dead time = max(t_off,HS, t_off,LS) plus margin.
Volt-Second Balance (Inductor)
In steady-state, the net volt-seconds applied across an inductor over one switching period must be zero. This constraint directly determines the duty cycle in all switched-mode converter topologies.
Phase Noise
A measure of frequency stability, expressed in dBc/Hz at a specified offset from the carrier. It is the single-sideband noise power in a 1 Hz bandwidth relative to the carrier power. Dominates timing jitter in high-speed clocking and RF systems.
Engineering Articles & Guidelines
Standards explainers and design guides are being added — check back soon, or browse component pages for per-part application guidance.
No spam. Unsubscribe anytime.