Overview

Inductor selection is where most buck converter designs go wrong — not because the math is hard, but because engineers use the wrong worst-case conditions. This guide walks through the full selection process for synchronous and non-synchronous buck converters operating between 200 kHz and 2 MHz: inductance calculation, ripple current, saturation margin, and copper losses, with a worked example and a decision between three real parts.

Inputs to Define First

ParameterWhy It MattersHow to Measure or Estimate
Vin_min, Vin_maxDefines the duty cycle range and peak voltage stressUse worst-case input voltage specs or measure under load and line variations
VoutSets target output voltage and duty cycleDefined by system requirements
Iout_maxDetermines average and peak inductor currentMax load current or worst-case transient
fswAffects ripple current and inductor sizeSelected switching frequency, typically 200 kHz–2 MHz
Ripple ratio (ΔIL / Iout)Controls ripple magnitude — impacts efficiency and transient responseChoose 20%–40% of Iout; 30% typical
Ambient temperature / thermal budgetAffects current rating and DCR lossesUse expected operating temperature and available PCB cooling

Selection Criteria

Inductance (L): [1]

L = (Vin_max - Vout) × D / (fsw × ΔIL)
    where D = Vout / Vin_max

Use Vin_max for the minimum inductance calculation — worst-case duty cycle produces the most ripple current for a given inductance.

Ripple current (ΔIL):

ΔIL = ripple_ratio × Iout_max    (target ripple_ratio: 0.20–0.40)

Peak current (Ipeak): [2]

Ipeak = Iout_max + ΔIL / 2

The inductor’s saturation current rating (Isat) must exceed Ipeak by at least 20%.

RMS current (Irms):

Irms = sqrt(Iout_max² + ΔIL² / 12)

Verify the inductor’s rated Irms ≥ calculated Irms.

Copper losses: [3]

Pcu = Irms² × DCR

Decision rules:

Worked Example

Design parameters:


Step 1 — Duty cycle at max input:

D = Vout / Vin_max = 3.3 / 14 = 0.236

Step 2 — Ripple current:

ΔIL = 0.30 × 3 A = 0.9 A

Step 3 — Minimum inductance:

L_min = (14 - 3.3) × 0.236 / (500,000 × 0.9)
      = 10.7 × 0.236 / 450,000
      = 2.525 / 450,000
      = 5.61 µH

Step 4 — Peak current:

Ipeak = 3 + 0.9 / 2 = 3.45 A

Step 5 — RMS current:

Irms = sqrt(3² + 0.9² / 12) = sqrt(9 + 0.0675) = sqrt(9.068) = 3.01 A

Step 6 — Part selection:

PartL (µH)Isat (A)DCR (mΩ)Pcu (W)Notes
SRR1260-100Y105.8480.435Oversized L; higher losses; large footprint
XAL1010-472ME4.7229.70.088Best efficiency; ample Isat margin
LPS4018-472MR4.7~14~120.110Compact alternative; slightly higher loss

With 4.7 µH chosen (lower than the 5.61 µH minimum), actual ripple current increases:

ΔIL = (14 - 3.3) × 0.236 / (500,000 × 4.7e-6)
    = 2.525 / 2.35
    = 1.075 A

Ipeak = 3 + 1.075 / 2 = 3.54 A    (XAL1010 Isat: 22 A — ample margin)

Decision: XAL1010-472ME is the right call here — lowest copper loss by a wide margin, and 22 A Isat gives plenty of headroom for transient spikes. LPS4018-472MR is a reasonable substitute if the XAL1010’s 10 × 10 mm footprint doesn’t fit. Avoid SRR1260-100Y in this application: 10 µH is more inductance than needed, the DCR is 5× higher, and you’re paying for it in heat.


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Common Mistakes

1. Sizing inductance to nominal Vin instead of max Vin. At high input voltage, duty cycle is shorter, so the inductor charges harder for the same on-time. Ripple current goes up, Ipeak goes up, and if you’re close to the saturation knee you’ll hit it under a transient. Size to Vin_max — it’s where ripple is worst. [1]

2. Treating Isat as a hard limit rather than a derating point. Isat is where inductance has dropped by some percentage — 10%, 20%, 30%, depending on the datasheet. At Isat you’re already on the nonlinear part of the B-H curve. A load transient on top of that pushes you into full saturation: inductance collapses, current spikes, and you’re troubleshooting a dead FET. Keep 20% margin above Ipeak. [2]

3. Chasing a very low ripple ratio. Below 0.1, you’re choosing inductance that’s larger than necessary — which means higher DCR, slower transient response, and a bigger footprint for no real gain. 20–40% is the practical range; 30% is a reasonable starting point for most designs.

4. Not calculating copper loss. DCR losses scale with Irms² and get worse as the inductor heats up — copper resistance increases about 0.4%/°C, so a hot inductor has higher losses than the room-temperature datasheet shows. If Pcu is approaching your thermal budget, pick a lower-DCR part, not a bigger heatsink. [3]

5. Missing Isat temperature derating. A part rated at 5.8 A at 25°C might saturate at 4.5 A at 100°C. This is in the datasheet, but it’s easy to miss if you only look at the headline spec. Check the derating curve for your operating temperature before signing off.

Layout and Thermal Notes

Keep the inductor close to the switching node and output capacitor — the loop formed by the FET, inductor, and output cap carries the full switching current and radiates in proportion to its area. Wide, short traces on both terminals. No signal routing through the switching loop. Ground plane continuity under the inductor matters: a slot or void increases loop inductance and makes the EMI problem worse. If the part is dissipating more than 0.1 W, copper pours and thermal vias under the pad help — the inductor’s DCR loss has to go somewhere, and “into the PCB” is better than “into the air.” Coilcraft’s AN-618 [4] is worth reading before laying out the switching node for the first time.

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Parts Referenced

Parts used in the worked example — check current stock and pricing:

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Sources

  1. Texas Instruments, Basic Calculation of a Buck Converter’s Power Stage, Application Report SLVA477B, 2014. Section 2.1: inductance calculation formula and ripple current ratio guidance.
  2. Coilcraft, Selecting Inductors for Buck Converters (Application Note). Saturation current margin recommendation and Isat definition at inductance roll-off.
  3. Würth Elektronik, DC-DC Converter Handbook, Chapter 3: inductor losses, DCR temperature coefficient, and thermal design.
  4. Coilcraft, PCB Layout Techniques for Buck Converters, AN-618. Switching loop minimization and inductor placement.